Omron CP - PROGRAMMING MANUAL 05-2007 Programming Manual page 345

Cp1h/cp1l cpu unit
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Data Shift Instructions
Operands
Operand Specifications
Description
312
C: Control Word
15
12
11
8
7
C
0
Always 0.
Data shifted into register
0 Hex: 0 shifted in
8 Hex: Contents of rightmost bit shifted in
Area
CIO Area
Work Area
Holding Bit Area
Auxiliary Bit Area
Timer Area
Counter Area
DM Area
Indirect DM addresses
in binary
Indirect DM addresses
in BCD
Constants
Data Registers
Index Registers
Indirect addressing
using Index Registers
NSLL(582) shifts D and D+1 (the shift words) by the specified number of
binary bits (specified in C) to the left (from the rightmost bit to the leftmost bit).
Either zeros or the value of the rightmost bit will be placed into the specified
number of bits of the shift word starting from the rightmost bit.
Lost
0
No. of bits to shift: 00 to 20 Hex
D
CIO 0 to CIO 6142
W0 to W510
H0 to H510
A448 to A958
T0000 to T4094
C0000 to C4094
D0 to D32766
@ D0 to @ D32767
*D0 to *D32767
---
---
---
,IR0 to ,IR15
–2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15
Shift n-bits
Contents of "a" or "0" shifted in
N bits
Section 3-8
C
CIO 0 to CIO 6143
W0 to W511
H0 to H511
A0 to A959
T0000 to T4095
C0000 to C4095
D0 to D32767
Specified values only
DR0 to DR15

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