Omron CP - PROGRAMMING MANUAL 05-2007 Programming Manual page 132

Sequence Input Instructions
Variations
Applicable Program Areas
Operand Specifications
Description
Flags
Precautions
Variations Creates ON Each Cycle OR NOT Result is ON
Creates ON Once for Upward Differentiation
Creates ON Once for Downward Differentiation
Immediate Refreshing Specification
Combined Refreshes Input Bit and Creates ON Once for
Variations Upward Differentiation
Refreshes Input Bit and Creates ON Once for
Downward Differentiation
Block program areas
OK OK
Area
CIO Area CIO 0.00 to CIO 6143.15
Work Area W0.00 to W511.15
Holding Bit Area H0.00 to H511.15
Auxiliary Bit Area A0.00 to A959.15
Timer Area T0000 to T4095
Counter Area C0000 to C4095
Task Flag Area TK00 to TK31
Condition Flags ER, CY, N, OF, UF, >, =, <, >=, <>, <=, A1, A0
Clock Pulses 0.02 s, 0.1 s, 0.2 s, 1 s, 1 min
TR Area ---
DM Area ---
Indirect DM addresses ---
in binary
Indirect DM addresses ---
in BCD
Constants ---
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers
–2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15
OR NOT is used for a normally closed bit connected in parallel. A normally
closed bit is configured to form a logical OR with a logic block beginning with a
LOAD or LOAD NOT instruction (connected to the bus bar or at the beginning
of the logic block). If there is no immediate refreshing specification, the speci-
fied bit in I/O memory is read. If there is an immediate refreshing specification,
the status of the CPU Unit's input terminal is read.
There are no flags affected by this instruction.
Immediate refresh (!) can be specified for OR NOT. An immediate refresh
instruction updates the status of the input bit from a CPU Unit built-in input
just before the instruction is executed.
Step program areas Subroutines
OK
OR NOT bit operand
Section 3-2
OR NOT
@OR NOT
%OR NOT
!OR NOT
!@OR NOT
!%OR NOT
Interrupt tasks
OK
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