Omron CP - PROGRAMMING MANUAL 05-2007 Programming Manual page 123

Sequence Input Instructions
Description
Flags
Precautions
90
Area
Indirect DM addresses ---
in binary
Indirect DM addresses ---
in BCD
Constants ---
Data Registers ---
Index Registers ---
Indirect addressing ,IR0 to ,IR15
using Index Registers
–2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
, –(– –)IR0 to, –(– –)IR15
LD is used for the first normally open bit from the bus bar or for the first nor-
mally open bit of a logic block. If there is no immediate refreshing specifica-
tion, the specified bit in I/O memory is read. If there is an immediate
refreshing specification, the status of the Basic Input Unit's input terminal is
read and used.
LD is used in the following circumstances as an instruction for indicating a log-
ical start.
• When directly connecting to the bus bar.
• When logic blocks are connected by AND LD or OR LD, i.e., at the begin-
ning of a logic block.
The AND LOAD and OR LOAD instructions are used to connect in series or in
parallel logic blocks beginning with LD or LD NOT.
At least one LOAD or LOAD NOT instruction is required for the execution con-
dition when output-related instructions cannot be connected directly to the
bus bar. If there is no LOAD or LOAD NOT instruction, a programming error
will occur with the program check by the CX-Programmer.
When logic blocks are connected by AND LOAD or OR LOAD instructions, the
total number of AND LOAD/OR LOAD instructions must match the total num-
ber of LOAD/LOAD NOT instructions minus 1. If they do not match, a pro-
gramming error will occur. For details, refer to 3-2-7 AND LOAD: AND LD and
3-2-8 OR LOAD: OR LD.
There are no flags affected by this instruction.
Differentiate up (@) or differentiate down (%) can be specified for LD. If differ-
entiate up (@) is specified, the execution condition is turned ON for one cycle
only after the status of the operand bit goes from OFF to ON. If differentiate
down (%) is specified, the execution condition is turned ON for one cycle only
after the status of the operand bit goes from ON to OFF.
Immediate refreshing (!) can be specified for LD. An immediate refresh
instruction updates the status of the input bit for CPU Unit built-in inputs just
before the instruction is executed.
For LD, it is possible to combine immediate refreshing and up or down differ-
entiation (!@ or !%). If either of these is specified, the built-in input is
refreshed from the CPU Unit just before the instruction is executed and the
execution condition is turned ON for one cycle only after the status goes from
OFF to ON, or from ON to OFF.
Section 3-2
LD operand bit