Omron CP - PROGRAMMING MANUAL 05-2007 Programming Manual page 304

Cp1h/cp1l cpu unit
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Data Movement Instructions
Variations
Applicable Program Areas
Operands
Operand Specifications
Description
Variations
Executed Each Cycle for ON Condition
Executed Once for Upward Differentiation
Executed Once for Downward Differentiation Not supported
Immediate Refreshing Specification
Block program areas
OK
D: Destination
The destination must be an Index Register (IR0 to IR15).
Area
CIO Area
Work Area
Holding Bit Area
Auxiliary Bit Area
Timer Area
Counter Area
Task Flag
DM Area
Indirect DM addresses
in binary
Indirect DM addresses
in BCD
Constants
Data Registers
Index Registers
Indirect addressing
using Index Registers
MOVR(560) finds the PLC memory address (absolute address) of S and
writes that address in D (an Index Register).
Internal I/O memory address of S
Index Register
If a timer or counter is specified in S, MOVR(560) will write the PLC memory
address of the timer/counter Completion Flag in D. Use MOVRW(561) to write
the PLC memory address of the timer/counter PV in D.
Step program areas
OK
OK
S
CIO 0 to CIO 6143
CIO 0.00 to CIO 6143.15
W0 to W511
W0.00 to W511.15
H0 to H511
H0.00 to H511.15
A0 to A447
A448 to A959
A0.00 to A447.15
A448.00 to A959.15
T0000 to T4095
(Completion Flag)
C0000 to C4095
(Completion Flag)
TK00 to TK31
D0 to D32767
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Section 3-7
MOVR(560)
@MOVR(560)
Not supported
Subroutines
Interrupt tasks
OK
D
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IR0 to IR15
271

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