Pci Host Bus Controller; Figure 2-10: 40-Pin Ide Connector - IEI Technology SPCIE-3600AM2 User Manual

SPCIE-3600AM2 PICMG 1.3 CPU Card

Figure 2-10: 40-pin IDE Connector

2.4.5 PCI Host Bus Controller

The NVIDIA MCP55Pro supports five PCI lanes. The PCI bus is compliant with the PCI
Revision 2.3 implementation. Some of the features of the PCI interface are listed below.
PCI rev. 2.3 specifications
5.0 V tolerant
Supports five external PCI slots at 33 MHz
o
PCI REQ/GNT pairs support
o
Five bus master arbitrations supported
PCI master and slave interfaces
Master-initiated and slave-initiated terminations supported
Bidirectional write posting support for concurrency
Flexible routing of all PCI interrupts
PCI bus errors such as data parity, command parity, and target aborts can be
programmed to generate Sync Flood on the HyperTransport interface
Supports read ahead—memory read line (MRL) and memory read multiple
(MRM)
Clock spread spectrum capability
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