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Summary of Contents for IEI Technology NANO-7240
- Page 1 NANO-7240 ULV CELERON 400 MHz CPU Board with Ethernet, VGA User’s Manual Version 1.0 August 31, 2005 ©Copyright 2005 by IEI Electronics Inc. All Rights Reserved.
- Page 2 Trademarks Nano-7240 is a registered trademark of ICP Electronics Inc., IBM PC is a registered trademark of International Business Machines Corporation. Intel is a registered trademark of Intel Corporation. AMIBIOS is registered trademarks of AMERICAN MEGATRENDS, INC.
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Page 3: Table Of Contents
Table of Contents CHAPTER 1 INTRODUCTION ..........1 1.1 S ..............2 PECIFICATIONS 1.2 B ............... 3 LOCK IAGRAM 1.3 P ............4 ACKAGE ONTENTS CHAPTER 2 INSTALLATION ..........5 2.1 N -7240 L ............5 AYOUT 2.2 LCD P ............ - Page 4 CHAPTER 4 BIOS SETUP............ 25 4.1 I ..............25 NTRODUCTION 4.2 S .............. 25 TARTING ETUP 4.3 U ..............26 SING ETUP 4.4 M ..............27 ..............27 4.4.1 Setup Items 4.5 S CMOS S ..........29 TANDARD ETUP 4.6 A BIOS F ..........
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Page 5: Chapter 1 Introduction
(VIA VT8606). An advanced high performance south bridge chip – VIA VT82C686B and super I/O W83877TF are also integrated in the Nano-7240 board. Four on-board UARTs are compatible with the NS16C550. The parallel port and IDE interface are compatible with IBM PC/AT architecture's. -
Page 6: Specifications
1.1 Specifications ® Onboard Intel ULV Celeron 400MHz ® TwisterT VT8606+ Super South Bridge Chipset VT82C686B Single PC100/133 SDRAM SO-DIMM, Memory supports up to 512 MB Ultra ATA33 IDE One PCI Enhance IDE hard drives. Interface Four High Speed Serial NS16C550 compatible UARTs, with 3 Ports RS232, 1 RS232/422/485. -
Page 7: Block Diagram
1.2 Block Diagram... -
Page 8: Package Contents
1.3 Package Contents In addition to this User's Manual, the Nano-7240 package includes the following items: One NANO-7240 ULV Celeron 400MHz Single Board Computer One IDE Cable (32200-008800) One Audio Cable (32000-000147) Three COM PORT Cable (32200-029600) One PRINTER Cable (32200-000050) -
Page 9: Chapter 2 Installation
Chapter 2 Installation 2.1 Nano-7240 Layout TOP SIDE... - Page 10 BOTTOM SIDE...
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Page 11: Lcd Power Setting
2.2 LCD Power setting JP2: This jumper is for the setting of LCD panel voltage. Description +3.3V JP1: This jumper is for the setting of LCD panel shift clock. Description Inverted Normal 2.3 Clear CMOS Setup If you want to clear the CMOS Setup (for example forgot the password you have to clear the setup and set the password again.), you should close the JP5 for about 3 seconds, then open again. -
Page 12: Compact Flash Card Mode Setting
2.4 Compact Flash Card Mode Setting JP4: Master/Slave Mode Setting Description OPEN SLAVE SHORT MASTER 2.5 ATX / AT Power Use Selection JP8: This jumper is for the setting of Power use selection. Description OPEN ATX Power CLOSE AT Power 2.6 RS-232/422/485 Setup JP13: RS-232/422/485 Setup (for COM4) JP13... -
Page 13: Chapter 3 Connection
Chapter 3 Connection This chapter describes how to connect peripherals, switches and indicators to the Nano-7240 board. Label Function DIMM1 SDR SODIM Connector FAN connector DIGITAL IO connector ATX Power connector LCD LVDS connector VGA connectors LCD TTL connectors PC/104 Plus Connector... -
Page 14: Pci Ide Disk Drive Connector
DATA 15 GROUND IDE DRQ GROUND IOW# GROUND IOR# GROUND IDE CHRDY GROUND IDE DACK GROUND–DEFAULT INTERRUPT HDC CS0# HDC CS1# HDD ACTIVE# GROUND GROUND Nano-7240 includes a slot for a Compact Flash Storage Card in IDE Mode (Using IDE2). - Page 15 J23: Compact Flash Storage Card Socket Description Description GROUND CARD DETECT1 CS1# CS3# GROUND IOR# IOW# OBLIGATORY TO PULL HIGH IRQ15 MASTER/SLAVE RESET# IORDY ACTIVE# PDIAG# CARD DETECT2 GROUND...
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Page 16: Fan Connector
3.2 Fan Connector Nano-7240 provides a CPU cooling fan connector. This connector can supply 12V/500mA to the cooling fan. In the connector there have a “rotation” pin. The rotation pin is to get the fan’s rotation signal to system. So the system BIOS could recognize the fan speed. Please note only specified fan offers the rotation signal. -
Page 17: Serial Ports
3.3 Serial Ports The Nano-7240 offers four high-speed NS16C550 compatible UARTs with Read/Receive 16 byte FIFO. J38: COM1 (RS-232 DB9 Connector) J36,J37: COM3,COM2(RS-232 ONLY) Description Description DCD3 DSR3 RTS3 CTS3 DTR3 J39: COM4(RS-232/485) Description Description DCD4 DSR4 RTS4 CTS4 DTR4... -
Page 18: Power Connector
3.4 Power Connector The pin assignments are as following: J33: External Power Connector PIN NO. Description +12V GROUND •J6: ATX Power connector PIN NO. Description 5VSB GROUND PSON 3.5 VGA Connector The pin assignments are as following. J8: CRT (15-pin Female Connector) Description Description GREEN... -
Page 19: Lcd Connector
3.6 LCD Connector The pin assignments are as following. J9: 50-pin Connector for TTL LCD Description Description FPD33 FPD34 FPD31 FPD35 FPD32 FPD30 FPD28 FPD29 FPD27 FPD25 FPD26 FPD24 FPD21 FPD23 FPD22 FPD16 FPD20 FPD17 FPD18 FPD19 FPD14 FPD13 FPD12 FPD15 FPD11 FPD7... -
Page 20: Irda Infrared Interface Port
ENVEE 3.7 IrDA Infrared Interface Port Nano-7240 built-in an IrDA port which support Serial Infrared (SIR) or Amplitude Shift Keyed IR (ASKIR) interface. When use the IrDA port have to set SIR or ASKIR mode in the BIOS’s Peripheral Setup’s COM2. -
Page 21: Usb Port Connector
3.8 USB Port Connector It complies with USB 1.1. USB3,4 are provided in 2x4 pin header and USB STD A Connector. J15,J32: USB Connector(USB1,2) Description Description USBVCC USBVCC USB0- USB1- USB0+ USB1+ J21: USB 3,4(2*4 Pin header) Description Description USBVCC1 USBGND2 USBGND1 USBVCC2... -
Page 22: Parallel Port Shared With Floppy
GROUND GROUND GROUND GROUND GROUND 3.11 DIGITAL IO Connector Nano-7240 provides built-in 8 DIGITAL IO pins that can be choose at the BIOS setup to be as Input or Output pins. J2: 8 BIT DIGITAL IO Connector Description Description VCC5... -
Page 23: 10/100M-Lan Rj45 Connector
Description Description 3.13 PC/104 Plus Connector Nano-7240 has a PC/104-Plus connector for both PC/104-Plus and PC/104 modules. The PCI bus of PC/104-Plus is a 32-bit bus running at 33MHz, and it is PCI2.1 compliant. J12: PC/104-Plus Connector (120-pin PCI bus) - Page 24 AD24 CBE3- AD26 AD29 AD30 REQ0- REQ2- GNT1- PCICLK0 PCICLK2 INTD- +12V INTA- REQ3- AD10 AD12 AD15 SBO- SDONE LOCK- DEVSEL- IRDY- CBE2- AD17 AD19 AD22 IDSEL1- IDSEL2 IDSEL3 AD25 AD28 AD27 AD31 REQ1- GNT0- GNT2- PCICLK1 PCICLK3 PCIRST-...
- Page 25 INTB- INTC- GNT3-...
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Page 26: Pc/104 Connector
3.14 PC/104 Connector J13: PC/104 Connector (64-pin ISA bus) Description Description IOCHK- RSTDRV IRQ9 DREQ2 ZWS- +12V IOCHRDY SMEMW- SA19 SMEMR- SA18 IOW- SA17 IOR- SA16 DACK3- SA15 DREQ3 SA14 DACK1- SA13 DREQ1 SA12 REFRESH- SA11 ISACLK SA10 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3... -
Page 27: Ps/2 Keyboard & Mouse Connector
J14: PC/104 Connector (40-pin ISA bus) Description Description SBHE- MCS16- SA23 IOCS16- SA22 IRQ10 SA21 IRQ11 SA20 IRQ12 SA19 IRQ15 SA18 IRQ14 SA17 DACK0- MEMR- DREQ0 MEMW- DACK5- DRREQ5 DACK6- SD10 DREQ6 SD11 DACK7- SD12 DREQ7 SD13 SD14 MASTER- SD15 3.15 PS/2 Keyboard &... -
Page 28: Sdr Sodimm
3.16 SDR SODIMM DIMM1: SDR SODIMM SOCKET 3.17 LED JP9:IDE LED PIN NO. Description IDE LED JP10:POWER LED PIN NO. Description 3.18 System Panel Connector J18: System Panel Connector Description Description PS_ON RESET VCC5 SPEAKER... -
Page 29: Chapter 4 Bios Setup
Chapter 4 BIOS Setup 4.1 Introduction This chapter discusses the Setup program written in the BIOS. It will give you a step-by-step guidance to configure your system. The user-defined configuration is then stored in battery-backed CMOS RAM, which retains the customized information while the power is off. 4.2 Starting Setup The BIOS is immediately active when you turn on the computer. -
Page 30: Using Setup
4.3 Using Setup In general, you can use the arrow keys to highlight items, press <Enter> to select, use the PageUp and PageDown keys to change entries and press <Esc> to quit. The following table provides more details about how to navigate in the Setup program using the keyboard. -
Page 31: Main Menu
4.4 Main Menu Once you enter the AMIBIOS™ CMOS Setup Utility, the Main Menu will appear on the screen. The Main Menu allows you to select from several setup functions and two exit choices. Use the arrow keys to go through the items and press <Enter> to accept and enter the sub-menu. - Page 32 Advanced CMOS Setup to configure system options. Advanced Chipset Setup: Advanced Chipset Setup to configure chipset features. Power Management Setup: Power Management Setup to configure power management features. PCI / Plug and Play Setup: Configures PCI / Plug and Play features. Peripheral Setup: Configures peripheral features.
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Page 33: Standard Cmos Setup
4.5 Standard CMOS Setup AMIBIOS SETUP – STANDARD CMOS SETUP (C)2001 American Megatrends, Inc. All Rights Reserved Date (mm/dd/yyyy): Tue Nov 10,2004 Base Memory: 639 KB Time (hh/mm/ss) : 20:27:10 Extd Memory: 495 MB Floppy Drive A: Not Installed Floppy Drive B: Not Installed LBA Blk PIO 32Bit... - Page 34 Primary/Secondary Master/Slave LBA Mode LBA (Logical Block Addressing) is a new IDE HDD access method to developed to overcome the 528-megabyte capacity bottleneck. If your IDE hard disk capacity is greater than 528MB, AMIBIOS can enable this LBA mode feature. The option is only for Primary Master IDE LBA mode.
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Page 35: Advanced Bios Features
4.6 Advanced BIOS Features AMIBIOS SETUP – ADVANCED CMOS SETUP (C)2001 American Megatrends, Inc. All Rights Reserved Quick Boot Enabled Available Options: 1st Boot Device Floopy Disabled 2nt Boot Device IDE-0 > Enabled 3rd Boot Device CD/DVD-0 Try Other Boot Devices Boot From Lan Disabled S.M.A.R.T. - Page 36 1st Boot Device This option sets the type of device for the first boot drives that the AMIBIOS attempts to boot from after AMIBIOS POST completes. The settings are Disabled, IDE-0, IDE-1, IDE-2, IDE-3, Floppy, ARMD-FDD, ARMD-HDD, CDROM, and SCSI. 2nd Boot Device This option sets the type of device for the second boot drives that the AMIBIOS attempts to boot from after AMIBIOS POST...
- Page 37 PS/2 Mouse Support When this option is enabled, BIOS supports a PS/2- type mouse. System Keyboard This option does not specify if a keyboard is attached to the computer. Rather, it specifies if error messages are displayed if a keyboard is not attached. This option permits you to configure workstation with no keyboard.
- Page 38 can be written to or read from the cache memory. Enabled: The contents of the video ROM area from C0000h – C7FFFh are copied (shadowed) from the ROM to the RAM for faster execution. C800,16k Shadow These options enable shadowing of the contents of the ROM area named in the option title.
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Page 39: Advanced Chipset Features
4.7 Advanced Chipset Features AMIBIOS SETUP – ADVANCED CHIPSET SETUP (C)2001 American Megatrends, Inc. All Rights Reserved ********* DRAM Timing ********* Available Options: Configure SDRAM Timing by SPD Disabled Disabled DRAM Frequency 133MHz > Enabled SDRAM CAS# Latency Memory Hole Disabled AGP Aperture Size 64MB... - Page 40 SDRAM CAS# Latency This controls the latency between the SDRAM read command and the time that the data actually becomes available. AGP Aperture Size This feature allows you to select the size of mapped memory for AGP graphic data. USB Controller Select Enabled if your system contains a Universal Serial Bus (USB) controller and you have USB peripherals.
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Page 41: Power Management Setup
4.8 Power Management Setup AMIBIOS SETUP – POWER MANAGEMENT SETUP (C)2001 American Megatrends, Inc. All Rights Reserved ACPI Aware O/S (S1) Available Options: Power Management/APM Enabled Video Power Down Mode Disabled > Yes Hard Disk Power Down Mode Disabled Standby Time Out (Minute) Disabled Suspend Time Out (Minute) Disabled... - Page 42 Power Management/APM Set this option to Enabled to run APM (Advanced Power Management). Video Power Down Mode Set this option to Enabled to allow the Video adapter and Monitor to be powered down by BIOS. Hard Disk Power Down Mode Set this option to Enabled to allow the IDE drive to be powered down by BIOS.
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Page 43: Pci / Plug And Play Setup
4.9 PCI / PLUG AND PLAY SETUP AMIBIOS SETUP – PCI / PLUG AND PLAY SETUP (C)2001 American Megatrends, Inc. All Rights Reserved Plug and Play Aware O/S Available Clear NVRAM Options: Onboard LAN Controller Enabled OnChip VGA Frame Buffer Size 32MB >... - Page 44 Plug and Play Aware O/S If enable, BIOS will configure only PnP ISA boot devices (i.e. all PnP ISA cards which has boot flag set). And PnP aware OS will configure all other devices. If disable, BIOS will configure all devices.
- Page 45 IRQ 3, 4, 5, 7, 9, 10, 11,14,15 To specify the bus that the specified IRQ line is used on. This option enables you to reserve IRQs for legacy ISA adapter cards. It determines if AMIBIOS should remove an IRQ from the pool of available IRQs passed to devices that are configurable by the system BIOS.
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Page 46: Peripheral Setup
4.10 Peripheral Setup AMIBIOS SETUP – PERIPHERAL SETUP (C)2001 American Megatrends, Inc. All Rights Reserved LPC Function Select Available Options: OnBoard FDC Enabled LPT(SPP) OnBoard Serial Port1 3F8/COM1 > FDC OnBoard Serial Port2 2F8/COM2 Serial Port2 Mode Normal Duplex Mode OnBoard Parallel Port Parallel Port Mode Normal... - Page 47 Parallel Port Mode This option specifies the parallel port mode. The settings are Normal, Bi-Dir, EPP, and ECP. Normal: The normal parallel port mode is used. Bi-Dir: Use this setting to support bi-directional transfers on the parallel port. EPP: The parallel port can be used with devices that adhere to the Enhanced.
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Page 48: Hardware Monitor Setup
On Board AC’97 Audio Enable or Disable AC’97 Audio Function. 4.11 Hardware Monitor Setup AMIBIOS SETUP – HARDWARE MONITOR SETUP (C)2001 American Megatrends, Inc. All Rights Reserved Chassis Intrusion Disabled Available Smart Fan Function Disabled Options: -= System Hardware Monitor =- >... -
Page 49: Change Supervisor Password
4.12 Change Supervisor Password You can set either supervisor or user password, or both of them. The differences between are: Supervisor password: You can enter and change the options of the setup menus with supervisor password. User password: You can only enter but do not have the right to change the options of the setup menus. -
Page 50: Appendix A: Watchdog Timer
Appendix A: Watchdog Timer The Watchdog Timer is provided to ensure that standalone systems can always recover from catastrophic conditions that cause the CPU to crash. This condition may have occurred by external EMI or a software bug. When the CPU stops working, hardware on the board will perform a hardware reset (cold boot) to bring the system back to a known state. - Page 51 W_LOOP: MOV DX, TIMER_STOP IN AL, DX MOV DX, TIMER_START IN AL, DX ;;RESTART COUNTER ;;ADD YOUR APPLICATION HERE CMP EXIT_AP, 0 JNE W_LOOP MOV DX, TIMER_STOP IN AL, DX ;;EXIT AP...
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Page 52: Appendix B: Address Mapping
Appendix B: Address Mapping I/O Address Map I/O Address Description 000-01F DMA Controller #1 020-021 Interrupt Controller # 1, Master 040-05F System Timer 060-06F Standard 101/102 keyboard Controller 070-07F Real time Clock, NMI Controller 080-0BF DMA Page Register 0A0-0BF Interrupt Controller # 2 0C0-0DF DMA Controller # 2 0F0-0F0... - Page 53 IRQ Mapping Chart IRQ0 System Timer IRQ8 RTC CMOS clock IRQ1 Keyboard IRQ9 ACPI STEERING IRQ2 IRQ Controller IRQ10 COM4 IRQ3 COM2 IRQ11 COM3 IRQ4 COM1 IRQ12 PS/2 mouse IRQ5 USB IRQ13 FPU IRQ6 FDC IRQ14 Primary IDE IRQ7 Printer IRQ15 Secondary IDE DMA Channel Assignment Channel...
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Page 54: Appendix C: How To Use Wake-Up Function
Appendix C: How to use Wake-Up Function The Nano-7240 provides two kind of Wake up Function. This page describes how to use Modem Wake-Up and LAN Wake-Up function. Wake-Up function is working while you use ATX power supply, Wake –Up On Modem(Ring): You must set the option Resume on Ring/LAN of CMOS SETUP to be enabled. -
Page 55: Appendix D: Digital Io
One of Digital circuit’s characteristics is its fast response to high or low signal. This kind of response is highly needed for harsh and critical industrial operating environment. Therefore, Nano-7240 is designed with 8-bit DIGITAL IO There are two kinds of signals (Input and Output) used by the DIGITAL IO function.
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