Data Transfer Operation; Data Transfer Cycle - Hitachi H8/500 Series Hardware Manual

• Note on Timing of DTE Modifications: The interrupt controller requires two system clock (ø)
periods to determine the priority level of an interrupt. Accordingly, when an instruction modifies
a data transfer enable register, the new setting does not take effect until the third state after that
instruction has been executed.

6.3 Data Transfer Operation

6.3.1 Data Transfer Cycle

When started by an interrupt, the DTC executes the following data transfer cycle:
1. From the DTC vector table, the DTC reads the address at which the register information table
for that interrupt is located in memory.
2. The DTC loads the data transfer mode register and source address register from this table and
reads the data (one byte or word) from the source address.
3. If so specified in the mode register, the DTC increments the source address register and writes
the new source address back to the table in memory.
4. The DTC loads the data transfer destination address register and writes the byte or word of data
to the destination address.
5. If so specified in the mode register, the DTC increments the destination address register and
writes the new destination address back to the table in memory.
6. The DTC loads the data transfer count register from the table in memory, decrements the data
count, and writes the new count back to memory.
7. If the data transfer count is now 0, the DTC generates a CPU interrupt. The interrupt vector is
the vector of the interrupt type that started the DTC.
At an appropriate point during this procedure the DTC also clears the interrupt request by clearing
the corresponding flag bit in the status register of the on-chip supporting module to "0." (For
IRQ or IRQ , the DTC clears an internal latch.)
0 1
But the DTC does not clear the data transfer enable bit in the data transfer enable register. This
action, if necessary, must be taken by the user-coded interrupt-handling routine invoked at the end
of the transfer.
The data transfer cycle is shown in a flowchart in figure 6-2.
For the steps from the occurrence of the interrupt up to the start of the data transfer cycle, see
section 5.4.1, "Interrupt Handling Flow."
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