Table of Contents
Advertisement
2. Mode 2
Figures E-3 and E-4 show how the pin states change when the RES pin goes Low during external
memory access in mode 2.
As soon as RES goes Low, all ports are initialized to the input (high-impedance) state. The AS,
DS, RD, and WR signals all go High. The data bus (D
to D
) is placed in the high-impedance
7
0
state. Pins P5
/A
to P5
/A
of the address bus are initialized as input ports.
7
15
0
8
Pins A
to A
of the address bus and the R/W signal are initialized 1.5 ø clock periods after the
7
0
Low state of the RES pin is sampled. Pins A
to A
are made Low. The signal is made High.
7
0
The clock output pins P1
/ø and P1
/E are initialized 0.5 ø clock periods after the Low state of the
0
1
RES pin is sampled. Both pins are initialized to the output state.
437
Downloaded from
Elcodis.com
electronic components distributor
Advertisement
Table of Contents
