Reset During Memory Access (Mode 3) - Hitachi H8/500 Series Hardware Manual

Masked-ROM Version
P1 / ø*
0
RES
Internal reset signal
A to A
19
R/W
AS, RD and DS (read)
WR and DS (write)
D to D (write)
7 0
I/O ports
*
The dotted line indicates that P1
but a clock output pin if the DDR bit is 1.
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0
Figure E-6 Reset during Memory Access (Mode 3)
External memory access
T T
1 2
/ø is an input port if the corresponding DDR bit is 0,
0
442
H'0000
High impedance
High impedance