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P1
n
Figure C-1 (f) Schematic Diagram of Port 1, Pins P1
Table C-1 (f) Port 1 Port Read (Pins P1
Setting
IRQ
E
0
or
= 1
IRQ
E
1
IRQ
E
0
or
= 0
IRQ
E
1
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RP1
, P1
5
Port Read Data
Pin value
DDR = 0
Pin value
DDR = 1
DR value
Reset
R
Q
D
P1 DDR
n
C
WP1D
Reset
R
Q
D
P1 DR
n
C
WP1
)
6
411
WP1D:
Write to P1DDR
WP1:
Write to Port 1
RP1:
Read Port 1
n:
5 or 6
Port 1 control register,
bits 5 and 6
IRQ E
0
or
IRQ E
1
Q
IRQ , IRQ to CPU
0
1
and P1
5
6
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