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B.2 Register Descriptions
Acronym of the register
SYSCR1—System Control Register 1
Bit
numbers
Bit
Initial bit
Initial value
values
Read/Write
Type of access permitted
R
Read only
W
Write only
R/W Both read and write
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Register name
7
6
5
—
IRQ
E
IRQ
E
1
0
1
0
0
—
R/W
R/W
Interrupt Request 0 Enable
0
P1
1
P1
Interrupt Request 1 Enable
0
P1
is an I/O port; IRQ
6
1
P1
is the IRQ
6
Address to which the
register is mapped
H'FEFC
4
3
2
NMIEG
BRLE
—
0
0
1
R/W
R/W
—
Bus Release Enable
0
P1
and P1
are I/O ports.
2
3
1
P1
is the BACK output pin. P1
2
Nonmaskable Interrupt Edge
0
An NMI request is generated on the falling edge of the NMI pin input.
1
An NMI request is generated on the rising edge of the NMI pin input.
is an I/O port; IRQ
input is disabled.
5
0
is the IRQ
input pin.
5
0
input is disabled.
1
input pin.
1
372
Name of the on-chip
supporting module
Port 1
1
0
Names of the
—
—
bits.
1
1
Dashes (—)
indicate
—
—
reserved bits.
is the BREQ input pin.
3
Full name of the bit
Functions of the bit settings
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