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18-2
Hardware Standby Sequence ·························································································313
19-1
(Maximum Synchronization Delay) ··············································································316
19-2
(Minimum Synchronization Delay) ···············································································317
20-1
Example of Circuit for Driving a Darlington Transistor Pair ········································322
20-2
Example of Circuit for Driving an LED ········································································322
20-3
Output Load Circuit ·······································································································325
20-4
Basic Bus Cycle (without Wait States) in Expanded Modes ·········································327
20-5
Basic Bus Cycle (with 1 Wait State) in Expanded Modes ·············································328
20-6
Bus Cycle Synchronized with E Clock ··········································································329
20-7
Reset Input Timing ········································································································ 330
20-8
Interrupt Input Timing ···································································································330
20-9
NMI Pulse Width (for Recovery from Software Standby Mode) ··································330
20-10
Bus Release State Timing ······························································································331
20-11
E Clock Timing ··············································································································331
20-12
Clock Oscillator Stabilization Timing ···········································································332
20-13
I/O Port Input/Output Timing ························································································333
20-14
Free-Running Timer Input/Output Timing ····································································334
20-15
External Clock Input Timing for Free-Running Timers ················································334
20-16
8-Bit Timer Output Timing ····························································································335
20-17
8-Bit Timer Clock Input Timing ····················································································335
20-18
8-Bit Timer Reset Input Timing ····················································································335
20-19
PWM Timer Output Timing ··························································································336
20-20
SCI Input Clock Timing ································································································336
20-21
SCI Input/Output Timing (Synchronous Mode) ····························································336
C-1 (f) Schematic Diagram of Port 1, Pins P1
C-1 (g) Schematic Diagram of Port 1, Pin P1
C-2
Schematic Diagram of Port 2 ·························································································413
C-3
Schematic Diagram of Port 3 ·························································································414
C-4
Schematic Diagram of Port 4 ·························································································415
C-5
Schematic Diagram of Port 5 ·························································································416
C-6
Schematic Diagram of Port 6 ·························································································417
C-7 (a) Schematic Diagram of Port 7, Pin P7
C-7 (b) Schematic Diagram of Port 7, Pins P7
C-7 (c) Schematic Diagram of Port 7, Pin P7
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0
··········································································407
1
···········································································408
2
··········································································409
3
···········································································410
4
···························································411
5
6
··········································································412
7
··········································································418
0
and P7
···························································419
1
2
··········································································420
3
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