1.1
Features ··································································································································1
1.2
Block Diagram ·······················································································································4
1.3
1.3.1 Pin Arrangement ·········································································································5
1.3.2 Pin Functions ··············································································································8
2.1
Overview ······························································································································23
2.2
Mode Descriptions ···············································································································24
2.3
Address Space Map ··············································································································25
2.3.1 Page Segmentation ····································································································25
2.4
3.1
Overview ······························································································································31
3.1.1 Features ·····················································································································31
3.1.2 Address Space ···········································································································32
3.2
CPU Register Descriptions ··································································································34
3.2.1 General Registers ······································································································34
3.2.2 Control Registers ······································································································35
3.3
Data Formats ························································································································41
3.4
Instructions ···························································································································44
3.4.2 Addressing Modes ····································································································45
3.5
Instruction Set ······················································································································50
3.5.1 Overview ···················································································································50
3.5.4 Logic Operations ·······································································································54
3.5.5 Shift Operations ········································································································55
3.5.6 Bit Manipulations ······································································································56
3.5.7 Branching Instructions ······························································································57
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