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Appendix C I/O Port Schematic Diagrams
C.1
Schematic Diagram of Port 1 ·····························································································407
C.2
Schematic Diagram of Port 2 ·····························································································413
C.3
Schematic Diagram of Port 3 ·····························································································414
C.4
Schematic Diagram of Port 4 ·····························································································415
C.5
Schematic Diagram of Port 5 ·····························································································416
C.6
Schematic Diagram of Port 6 ·····························································································417
C.7
Schematic Diagram of Port 7 ·····························································································418
C.8
Schematic Diagram of Port 8 ·····························································································423
C.9
Schematic Diagram of Port 9 ·····························································································424
Appendix D Memory Map
Appendix E Pin State
E.1
Port State of Each Pin State ·······························································································431
E.2
Pin Stattus in the Reset State ······························································································434
Appendix F Timing of Entry to and Recovery from Hardware Standby Mode
Appendix G Package Dimensions
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