Hitachi H8/500 Series Hardware Manual page 383

P1CR—Port 1 Control Register
Bit
Initial value
Read/Write
P2DDR—Port 2 Data Direction Register
Bit
Initial value
Read/Write
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7 6 5
— IRQ E IRQ
1
1 0 0
— R/W R/W
Interrupt Request 0 Enable
0 P1
1 P1
Interrupt Request 1 Enable
0 P1 is an I/O port; input is disabled.
6
1 P1 is the input pin.
6
7 6 5
— — —
1 1 1
— — —
H'FFFC
4 3
E NMIEG BRLE
0
0 0
R/W R/W
Bus Release Enable
0 P1
1 P1
Nonmaskable Interrupt Edge
0 An NMI request is generated on the
falling edge of the NMI pin input.
1 An NMI request is generated on the
rising edge of the NMI pin input.
is an I/O port; input is disabled.
5
is the input pin.
5
H'FF81
4 3
P2 DDR P2 DDR P2
4 3
0 0
W W
374
2 1
— —
1 1
— —
and P1 are I/O ports.
2 3
is the output pin and
2
P1 is the input pin.
3
2 1
DDR P2 DDR P2
2 1
0 0
W W
Port 2 Input/Output Selection
0 Input port
1 Output port
Port 1
0
—
1
—
Port 2
0
DDR
0
0
W