Table of Contents
Advertisement
LTM4700
APPLICATIONS INFORMATION
TYPE II COMPENSATION
GAIN
Figure 29. R
CHECKING TRANSIENT RESPONSE
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
amount equal to ∆I
LOAD(ESR)
series resistance of C
. ∆I
OUT
discharge C
generating the feedback error signal that
OUT
forces the regulator to adapt to the current change and
return V
to its steady-state value. During this recovery
OUT
time V
can be monitored for excessive overshoot or
OUT
ringing, which would indicate a stability problem. The
availability of the COMP pin not only allows optimization of
control loop behavior but also provides a DC-coupled and
AC-filtered closed-loop response test point. The DC step,
rise time and settling at this test point truly reflects the
closed-loop response. Assuming a predominantly second
order system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining the
rise time at the pin. The COMPna external capacitor shown
in the Typical Applications circuit will provide an adequate
starting point for most applications. The programmable
parameters that affect loop gain are the voltage range, bit[1]
of the MFR_PWM_CONFIG command, the current range
bit[7] of the MFR_PWM_MODE command, the g
PWM channel amplifier bits [7:5] of MFR_PWM_COMP,
and the internal R
compensation resistor, bits[4:0]
COMP
of MFR_PWM_COMP. Be sure to establish these settings
prior to compensation calculation.
58
INCREASE R
COMP
FREQUENCY
4700 F28
Adjust
TH
shifts by an
OUT
, where ESR is the effective
also begins to charge or
LOAD
of the
m
For more information
The COMPna series internal R
filter sets the dominant pole-zero loop compensation. The
internal R
value can be modified (from 0Ω to 62kΩ)
COMP
using bits[4:0] of the MFR_PWM_ COMP command. Adjust
the value of R
to optimize transient response once the
COMP
final PCB layout is done and the particular C
capacitor and output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1µs to 10µs will
produce output voltage and COMP pin waveforms that will
give a sense of the overall loop stability without break-
ing the feedback loop. Placing a power MOSFET with a
resistor to ground directly across the output capacitor
and driving the gate with an appropriate signal generator
is a practical way to produce to a load step. The MOSFET
+ R
will produce output currents approximately
SERIES
equal to V
/R
. R
OUT
SERIES
are valid depending on the current limit settings and the
programmed output voltage. The initial output voltage step
resulting from the step change in output current may not
be within the bandwidth of the feedback loop, so this signal
cannot be used to determine phase margin. This is why
it is better to look at the COMP pin signal which is in the
feedback loop and is the filtered and compensated control
loop response. The gain of the loop will be increased by
increasing R
and the bandwidth of the loop will be
COMP
increased by decreasing C
by the same factor that C
quency will be kept the same, thereby keeping the phase
shift the same in the most critical frequency range of the
feedback loop. The gain of the loop will be proportional
to the transconductance of the error amplifier which is
set using bits[7:5] of the MFR_PWM_COMP command.
The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance. A second, more
severe transient is caused by switching in loads with large
(>1µF) supply bypass capacitors. The discharged bypass
capacitors are effectively put in parallel with C
a rapid drop in V
. No regulator can alter its delivery of
OUT
current quickly enough to prevent this sudden step change
www.analog.com
and external C
COMP
COMPna
COMPbn
values from 0.1Ω to 2Ω
SERIES
. If R
is increased
COMPna
COMP
is decreased, the zero fre-
TH
, causing
OUT
filter
Rev. B
Advertisement
Table of Contents
