Analog Devices Linear LTM 4700 User Manual page 64

LTM4700
APPLICATIONS INFORMATION
parameters defined by JESD51-12 or provided in the
Pin Configuration section replicates or conveys normal
operating conditions of a µModule regulator. For example,
in normal board-mounted applications, never does 100%
of the device's total power loss (heat) thermally conduct
exclusively through the top or exclusively through bot-
tom of the µModule package—as the standard defines
for θ and θ , respectively. In practice, power
JCtop JCbottom
loss is thermally dissipated in both directions away from
the package—granted, in the absence of a heat sink and
airflow, a majority of the heat flow is into the board.
Within the LTM4700, be aware there are multiple power
devices and components dissipating power, with a con-
sequence that the thermal resistances relative to different
junctions of components or die are not exactly linear with
respect to total package power loss. To reconcile this
complication without sacrificing modeling simplicity—but
also, not ignoring practical realities—an approach has been
taken using FEA software modeling along with laboratory
testing in a controlled-environment chamber to reasonably
define and correlate the thermal resistance values supplied
in this data sheet: (1) Initially, FEA software is used to ac-
curately build the mechanical geometry of the LTM4700
Figure 35. Thermal Image, LTM4700 Running from 12V Input to 1V Output, 100A Output with 200LFM Airflow, No Heat Sinking
64
and the specified PCB with all of the correct material
coefficients along with accurate power loss source defini-
tions; (2) this model simulates a software-defined JEDEC
environment consistent with JESD51-9 and JESD51-12
to predict power loss heat flow and temperature readings
at different interfaces that enable the calculation of the
JEDEC-defined thermal resistance values; (3) the model
and FEA software is used to evaluate the LTM4700 with
heat sink and airflow; (4) having solved for and analyzed
these thermal resistance values and simulated various
operating conditions in the software model, a thorough
laboratory evaluation replicates the simulated conditions
with thermocouples within a controlled environment
chamber while operating the device at the same power
loss as that which was simulated. The outcome of this
process and due diligence yields the set of derating curves
provided in later sections of this data sheet, along with
well-correlated JESD51-12-defined θ values provided in
the Pin Configuration section of this data sheet.
The 0.8V, 1.2V and 1.8V power loss curves in Figure 36,
Figure 37 and Figure 38 respectively can be used in co-
ordination with the load current derating curves in Figure
39 to Figure 44 for calculating an approximate θ
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thermal
JA
Rev. B