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APPLICATIONS INFORMATION
EMI PERFORMANCE
The SWn pin provides access to the midpoint of the power
MOSFETs in LTM4700's power stages.
Connecting an optional series RC network from SWn to
GND can dampen high frequency (~30MHz+) switch node
ringing caused by parasitic inductances and capacitances
in the switched-current paths. The RC network is called
a snubber circuit because it dampens (or "snubs") the
resonance of the parasitics, at the expense of higher power
loss. To use a snubber, choose first how much power to
allocate to the task and how much PCB real estate is avail-
able to implement the snubber. For example, if PCB space
allows a low inductance 0.5W resistor to be used then the
capacitor in the snubber network (CSW) is computed by:
P
SNUB
C
=
SW
2
V
• f
IN n (MAX)
SW
where V
is the maximum input voltage that the
INn(MAX)
input to the power stage (V
and f
is the DC/DC converter's switching frequency
SW
of operation. C
should be NPO, C0G or X7R-type (or
SW
better) material.
The snubber resistor (R
SW
5nH
R
=
SW
C
SW
The snubber resistor should be low ESL and capable of
withstanding the pulsed currents present in snubber cir-
cuits. A value between 0.7Ω and 4.2Ω is normal.
A 2.2nF snubber capacitor is a good value to start with in
series with the snubber resistor to gnd. The no load input
quiescent current can be monitored while selecting different
RC series snubber components to get a increased power
loss versus switch node ringing attenuation.
) will see in the application,
INn
) value is then given by:
For more information
SAFETY CONSIDERATIONS
The LTM4700 modules do not provide galvanic isolation
to V
. There is no internal fuse. If required,
from V
IN
OUT
a slow blow fuse with a rating twice the maximum input
current needs to be provided to protect each unit from
catastrophic failure.
The fuse or circuit breaker should be selected to limit the
current to the regulator during overvoltage in case of an
internal top MOSFET fault. If the internal top MOSFET fails,
then turning it off will not resolve the overvoltage, thus
the internal bottom MOSFET will turn on indefinitely trying
to protect the load. Under this fault condition, the input
voltage will source very large currents to ground through
the failed internal top MOSFET and enabled internal bot-
tom MOSFET. This can cause excessive heat and board
damage depending on how much power the input voltage
can deliver to this system. A fuse or circuit breaker can be
used as a secondary fault protector in this situation. The
device does support over current and overtemperature
protection.
LAYOUT CHECKLIST/EXAMPLE
The high integration of LTM4700 makes the PCB board
layout very simple and easy. However, to optimize its electri-
cal and thermal performance, some layout considerations
are still necessary.
Use large PCB copper areas for high current paths,
n
including V
, GND and V
INn
the PCB conduction loss and thermal stress.
Place high frequency ceramic input and output capaci-
n
tors next to the V
, GND and V
INn
high frequency noise.
Place a dedicated power ground layer underneath the
n
module.
To minimize the via conduction loss and reduce module
n
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
www.analog.com
LTM4700
. It helps to minimize
OUTn
pins to minimize
OUTn
Rev. B
69
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