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OPERATION
primarily to the MFR_FAULT_LOG command. The timeout
period defaults to 32ms.
The user is encouraged to use as high a clock rate as
possible to maintain efficient data packet transfer between
all devices sharing the serial bus interface. The LTM4700
supports the full PMBus frequency range from 10kHz
to 400kHz.
SIMILARITY BETWEEN PMBus, SMBus AND I
2-WIRE INTERFACE
The PMBus 2-wire interface is an incremental extension
of the SMBus. SMBus is built upon I
differences in timing, DC parameters and protocol. The
PMBus/SMBus protocols are more robust than simple
2
I
C byte commands because PMBus/SMBus provide
timeouts to prevent persistent bus errors and optional
packet error checking (PEC) to ensure data integrity. In
general, a master device that can be configured for I
communication can be used for PMBus communication
with little or no change to hardware or firmware. Repeat
start (restart) is not supported by all I
is required for SMBus/PMBus reads. If a general purpose
2
I
C controller is used, check that repeat start is supported.
The LTM4700 supports the maximum SMBus clock speed
of 100kHz and is compatible with the higher speed PMBus
specification (between 100kHz and 400kHz) if MFR_ COM-
MON polling or clock stretching is enabled. For robust
communication and operation refer to the Note section
in the PMBus Command Summary. Clock stretching is
enabled by asserting bit 1 of MFR_CONFIG_ALL.
For a description of the minor extensions and exceptions
PMBus makes to SMBus, refer to PMBus Specification
Part 1 Revision 1.2: Paragraph 5: Transport.
For a description of the differences between SMBus and
2
I
C, refer to System Management Bus (SMBus) Speci-
fication Version 2.0: Appendix B—Differences Between
2
SMBus and I
C.
PMBus SERIAL DIGITAL INTERFACE
The LTM4700 communicates with a host (master) using the
standard PMBus serial bus interface. The Timing Diagram,
Figure 6, shows the timing relationship of the signals on
the bus. The two-bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources are required on these lines. The LTM4700
is a slave device. The master can communicate with the
LTM4700 using the following formats:
2
C
n
n
2
C with some minor
The following PMBus protocols are supported:
n
n
n
2
C
Figure 7 to Figure 24 illustrate the aforementioned PMBus
protocols. All transactions support PEC and GCP (group
command protocol). The Block Read supports 255 bytes
2
C controllers but
of returned data. For this reason, the PMBus timeout may
be extended when reading the fault log.
Figure 7 is a key to the protocol diagrams in this section.
PEC is optional.
A value shown below a field in the following figures is
mandatory value for that field.
The data formats implemented by PMBus are:
n
n
n
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Master Transmitter, Slave Receiver
Master Receiver, Slave Transmitter
Write Byte, Write Word, Send Byte
Read Byte, Read Word, Block Read, Block Write
Alert Response Address
Master transmitter transmits to slave receiver. The
transfer direction in this case is not changed.
Master reads slave immediately after the first byte. At
the moment of the first acknowledgment (provided by
the slave receiver) the master transmitter becomes
a master receiver and the slave receiver becomes a
slave transmitter.
Combined format. During a change of direction within
a transfer, the master repeats both a start condition
and the slave address but with the R/W bit reversed. In
this case, the master receiver terminates the transfer
by generating a NACK on the last byte of the transfer
and a STOP condition.
LTM4700
Rev. B
39
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