Test Circuits - Analog Devices Linear LTM 4700 User Manual

TEST CIRCUITS

Test Circuit 1. LTM4700 ATE High V
V 5.75V TO 16V
IN
150µF
22µF
×6
ON/OFF CONTROL
FAULT INTERRUPTS
SYNCHRONIZATION
TIME-BASE
REGISTER WRITE
PROTECTION
Test Circuit 2. LTM4700 ATE Low V
SV
IN
V
4.5V TO 5.75V
IN
150µF
22µF
×6
ON/OFF CONTROL
FAULT INTERRUPTS
SYNCHRONIZATION
TIME-BASE
REGISTER WRITE
PROTECTION
2.2µF
+
IN
R
SENSE
–
IN
V
IN1
V
IN0
SV
IN
SV
IN
RUN1
RUN0
FAULT0
FAULT1
SYNC
SHARE_CLK
WP
2200pF
2200pF
100pF
1
2.2µF
+
IN
R
SENSE
–
IN
V
IN1
V
IN0
SV
IN
SV
IN
RUN1
RUN0
FAULT0
FAULT1
SYNC
SHARE_CLK
WP
2200pF 2200pF
100pF
For more information
Operating Range Configuration, 5.75V ≤ V
IN
4.7µF
SW0
V
OUT0
V
OSNS0
V
OSNS0
SW1
V
OUT1
V
LTM4700
OSNS1
V
OSNS1
SCL
SDA
ALERT
GND
SGND
4700 TC01
100pF
Operating Range Configuration, 4.5V ≤ V
IN
4.7µF
SW0
V
OUT0
V
OSNS0
V
OSNS0
SW1
V
OUT1
V
LTM4700
OSNS1
V
OSNS1
SCL
SDA
ALERT
GND
SGND
4678 TC02
100pF
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LTM4700
≤ 16V
IN
V
OUT0
+ 1V, ADJUSTABLE
UP TO 50A
100µF
LOAD0
×4
–
C * BULK
OUT0
V
OUT1
+
1V, ADJUSTABLE
UP TO 50A
100µF
LOAD1
×4
C * BULK
–
OUT1
2
I C/SMBus I/F WITH PMBus COMMAND SET
TO/FROM IPMI OR OTHER BOARD
MANAGEMENT CONTROLLER
*C AND C ARE
OUT0 OUT1
OPTIONAL FOR ATE TEST
(PULL-UP RESISTORS ON DIGITAL
I/O PINS NOT SHOWN)
≤ 5.75V
IN
V
OUT0
1V, ADJUSTABLE
+
UP TO 50A
100µF
LOAD0
×4
–
C * BULK
OUT0
V
OUT1
+
1V, ADJUSTABLE
100µF UP TO 50A
LOAD1
×4
C * BULK
–
OUT1
2
I C/SMBus I/F WITH PMBus COMMAND SET
TO/FROM IPMI OR OTHER BOARD
MANAGEMENT CONTROLLER
*C AND C ARE
OUT0 OUT1
OPTIONAL FOR ATE TEST
(PULL-UP RESISTORS ON DIGITAL
I/O PINS NOT SHOWN)
Rev. B
21