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LTM4700
PIN FUNCTIONS
+
+
V
(P14), V
OSNS0
OSNS1
age Sense Input. Together, V
kelvin-sense the output voltage at the point of load (POL)
and provide the differential feed-back signal directly to
the feedback loop. Command V
voltage by serial bus. Its initial command value at SV
power-up is dictated by NVM (non-volatile memory)
contents (factory default: 1.000V) or, optionally, may be
set by configuration resistors; see VOUTn_CFG and the
Applications Information section.
INTV
(R10): Internal Regulator, 5.5V Output. When
CC
operating the LTM4700 from 5.75V ≤ SV
generates INTV
from SV
CC
and the MOSFET drivers of the LTM4700. No external
decoupling is required. INTV
the RUNn pin state. When operating the LTM4700 with
4.5V ≤ SV
< 5.75V, INTV
IN
to SVIN.
+
I
(R13): Positive Current Sense Amplifier Input. If the
IN
input current sense amplifier is not used, this pin must be
–
shorted to the I
and SV
IN
formation section for detail about the input current sensing.
PGOOD0 (R14), PGOOD1 (N9): Power Good Indicator
Outputs. Open-drain logic output that is pulled to ground
when the output exceeds the UV and OV regulation win-
dow. The output is deglitched by an internal 100µs filter.
A pull-up resistor to 3.3V is required in the application.
18
(M9): Positive Differential Volt-
+
–
and V
serve to
OSNSn
OSNSn
's target regulation
OUTn
≤ 16V, an LDO
IN
to bias internal control circuits
IN
is regulated regardless of
CC
must be electrically shorted
CC
pins. See the Applications In-
IN
For more information
V
(U12-AB12, U13-AB13, U14-AB14, N15-AB15),
OUT0
V
(A12-F12, A13-F13, A14-F14, A15-K15): Power
OUT1
Output Pins of the Switching Mode Regulator. Apply out-
put load between these pins and GND pins. Recommend
placing output decoupling capacitance directly between
these pins and GND pins.
IN
SV
(V9): Input Supply for LTM4700's Internal Control
IN
IC and for the Internal 5V Bias Circuitry. In most applica-
tions, SV
connects to V
IN
operated from an auxiliary supply separate from V
for powering the V
IN0
The SV
is also connected to an internal 5V bias circuit
IN
which intend to replace the internal LDO when the SVIN
is higher than 7V. This internal bias circuitry can be turn
on by pulling RUNP pin high. When operating from 4.5V
to 5.75V input, then the main input supply should connect
to SV
and INTV
IN
CC
RUNP (Y10): This pin enables the on board bias circuit to
supply IC and to drive the MOSFET when the SV
than 7V. Tie to ground to disable the bias circuit when V
is less than 5.75V. See Applications Information section.
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and/or V
. SV
IN0
IN1
/V
from a lower supply like 3.3V.
IN1
with RUNP pin grounded.
can be
IN
/V
IN0
IN1
is higher
IN
IN
Rev. B
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