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LTM4700
PIN FUNCTIONS
A resistor connected from this pin to SGND, in combination
with resistor pin settings on V
factory-default NVM setting of MFR_CONFIG_ALL[6] = 0b
can be used to configure the LTM4700's Channel 0 output
to power-up to a VOUT_COMMAND value (and associated
output voltage monitoring and protection/fault-detection
thresholds) different from those of NVM contents. (See the
Applications Information section.) Connecting resistor(s)
from V
to SGND and/or V
OUT0_CFG
this manner allows a convenient way to configure multiple
LTM4700s with identical NVM contents for different output
voltage settings all without GUI intervention or the need to
"custom-pre-program" module NVM contents. Minimize
capacitance, especially when the pin is left open, to as-
sure accurate detection of the pin state. Note that use of
RCONFIGs on V
/V
OUT0_CFG
range setting (MFR_PWM_MODE0[1]) and loop gain.
FSWPH_CFG (J11): Switching Frequency, Channel Phase-
Interleaving Angle and Phase Relationship to SYNC Con-
figuration Pin. If this pin is left open—or, if the LTM4700
is configured to ignore pin-strap (R
i.e., MFR_CONFIG_ALL[6] = 1b—then the LTM4700's
switching frequency (FREQUENCY_SWITCH) and chan-
nel phase relation-ships (with respect to the SYNC clock;
MFR_PWM_CONFIG[2:0]) are dictated at SV
according to the LTM4700's NVM contents. Default factory
values are: 350kHz operation; Channel 0 at 0°; and Chan-
nel 1 at 180°C (convention throughout this document: a
phase angle of 0° means the channel's switch node rises
coincident with the falling edge of the SYNC pulse). Con-
necting a resistor from this pin to SGND (and using the
factory-default NVM setting of MFR_CONFIG_ALL[6] = 0b)
allows a convenient way to configure multiple LTM4700s
with identical NVM contents for different switching frequen-
cies of operation and phase interleaving angle settings of
intra- and extra-module-paralleled channels—all, without
GUI intervention or the need to "custom pre-program"
module NVM contents. (See the Applications Information
section.) Minimize capacitance—especially when the pin
is left open—to assure accurate detection of the pin state.
16
, and using the
TRIM0_CFG
to SGND in
TRIM0_CFG
can affect the V
TRIM0_CFG
) resistors,
CONFIG
power-up
IN
For more information
RUN0 (J12), RUN1 (K12): Enable Run Input for Channels
0 and 1, Respectively. Open-drain input and output. Logic
high on these pins enables the respective outputs of the
LTM4700. These open-drain output pins hold the pin low
until the LTM4700 is out of reset and SV
exceed VIN_ON. A pull-up resistor to 3.3V is required in
the application. The LTM4700 pulls RUN0 and/or RUN1
low, as appropriate, when a global fault and/or channel-
specific fault occurs whose fault response is configured to
latch off and cease regulation; issuing a CLEAR_FAULTS
2
command via I
C or power-cycling SV
restart the module, in such cases. Do not pull RUN logic
high with a low impedance source.
ALERT (J13): Open-Drain Digital Output. A pull-up resistor
to 3.3V is required in the application only if SMBALERT
OUT0
interrupt detection is implemented in one's SMBus system.
SCL (J14): Serial Bus Clock Open-Drain Input (Can Be an
Input and Output, if Clock Stretching is Enabled). A pull-up
resistor to 3.3V is required in the application for digital com-
munication to the SMBus master(s) that nominally drive
this clock. The LTM4700 will never encounter scenarios
where it would need to engage clock stretching unless SCL
communication speeds exceed 100kHz—and even then,
LTM4700 will not clock stretch unless clock stretching
is enabled by means of setting MFR_CONFIG_ALL[1] =
1b. The factory-default NVM configuration setting has
MFR_CONFIG_ALL[1] = 0b: clock stretching disabled. If
communication on the bus at clock speeds above 100kHz
is required, the user's SMBus master(s) need to implement
clock stretching support to assure solid serial bus commu-
nications, and only then should MFR_CONFIG_ALL[1] be
set to 1b. When clock stretching is enabled, SCL becomes
a bidirectional, open-drain output pin on LTM4700.
SHARE_CLK (K8): Share Clock, Bidirectional Open-Drain
Clock Sharing Pin. Nominally 100kHz. Used for synchro-
nizing the time base between multiple LTM4700s (and
any other Analog Devices parts with a SHARE_CLK pin)
to realize well-defined rail sequencing and rail tracking.
Tie the SHARE_CLK pins of all such devices together; all
devices with a SHARE_CLK pin will synchronize to the
fastest clock. A pull-up resistor to 3.3V is required.
www.analog.com
is detected to
IN
is necessary to
IN
Rev. B
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