Xilinx KC705 User Manual page 77

NET FLASH_D12
NET PHY_CRS
NET FLASH_D13
NET FLASH_D14
NET FLASH_D15
NET PHY_RXCTL_RXDV
NET PHY_RXD7
NET PHY_RXD6
NET PHY_RXD5
NET PHY_RXCLK
NET PHY_RXD3
NET PHY_RXD2
NET PHY_RXD1
NET FLASH_WAIT
NET PHY_RXD0
NET PHY_RXER
NET FLASH_A15
NET FLASH_A14
NET FLASH_A13
NET FLASH_A12
NET FLASH_A11
NET FLASH_A10
NET FLASH_A9
NET FLASH_A8
NET FLASH_A7
NET SM_FAN_TACH
NET FLASH_A6
NET FLASH_A5
NET FLASH_A4
NET FLASH_A3
NET FLASH_A2
NET FLASH_A1
NET FLASH_A0
NET PHY_COL
NET USB_TX
NET XADC_VAUX0P_R
NET XADC_VAUX0N_R
NET XADC_VAUX8P_R
NET XADC_VAUX8N_R
NET USB_RTS
NET USB_RX
NET IIC_SDA_MAIN
NET IIC_SCL_MAIN
NET PHY_MDIO
NET FMC_LPC_PRSNT_M2C_B_LS
NET FMC_HPC_PRSNT_M2C_B_LS
NET PHY_RESET
NET FMC_HPC_PG_M2C_LS
NET FMC_C2M_PG_LS
NET FMC_VADJ_ON_B_LS
NET PHY_TXD7
NET PHY_TXD6
NET PHY_TXC_GTXCLK
NET PHY_TXD5
NET PHY_TXD4
NET SM_FAN_PWM
NET USB_CTS
NET USER_SMA_CLOCK_P
NET USER_SMA_CLOCK_N
NET USER_CLOCK_P
NET USER_CLOCK_N
NET PHY_TXCLK
NET PHY_TXD3
NET PHY_TXD2
NET FLASH_ADV_B
NET PHY_TXD0
NET PHY_TXCTL_TXEN
NET PHY_TXER
NET PHY_INT
NET PHY_TXD1
NET FLASH_A23
NET FLASH_A22
NET FLASH_A21
NET FLASH_A20
NET FLASH_A19
NET IIC_MUX_RESET_B
NET FLASH_A18
NET FLASH_A17
NET FLASH_A16
NET FLASH_OE_B
NET FLASH_FWE_B
KC705 Evaluation Board
UG810 (v1.3) May 10, 2013
LOC = P28 | IOSTANDARD=LVCMOS25; # Bank
LOC = R30 | IOSTANDARD=LVCMOS25; # Bank
LOC = T30 | IOSTANDARD=LVCMOS25; # Bank
LOC = P26 | IOSTANDARD=LVCMOS25; # Bank
LOC = R26 | IOSTANDARD=LVCMOS25; # Bank
LOC = R28 | IOSTANDARD=LVCMOS25; # Bank
LOC = T28 | IOSTANDARD=LVCMOS25; # Bank
LOC = T26 | IOSTANDARD=LVCMOS25; # Bank
LOC = T27 | IOSTANDARD=LVCMOS25; # Bank
LOC = U27 | IOSTANDARD=LVCMOS25; # Bank
LOC = U28 | IOSTANDARD=LVCMOS25; # Bank
LOC = T25 | IOSTANDARD=LVCMOS25; # Bank
LOC = U25 | IOSTANDARD=LVCMOS25; # Bank
LOC = U29 | IOSTANDARD=LVCMOS25; # Bank
LOC = U30 | IOSTANDARD=LVCMOS25; # Bank
LOC = V26 | IOSTANDARD=LVCMOS25; # Bank
LOC = V27 | IOSTANDARD=LVCMOS25; # Bank
LOC = V29 | IOSTANDARD=LVCMOS25; # Bank
LOC = V30 | IOSTANDARD=LVCMOS25; # Bank
LOC = V25 | IOSTANDARD=LVCMOS25; # Bank
LOC = W26 | IOSTANDARD=LVCMOS25; # Bank
LOC = V19 | IOSTANDARD=LVCMOS25; # Bank
LOC = V20 | IOSTANDARD=LVCMOS25; # Bank
LOC = W23 | IOSTANDARD=LVCMOS25; # Bank
LOC = W24 | IOSTANDARD=LVCMOS25; # Bank
LOC = U22 | IOSTANDARD=LVCMOS25; # Bank
LOC = U23 | IOSTANDARD=LVCMOS25; # Bank
LOC = V21 | IOSTANDARD=LVCMOS25; # Bank
LOC = V22 | IOSTANDARD=LVCMOS25; # Bank
LOC = U24 | IOSTANDARD=LVCMOS25; # Bank
LOC = V24 | IOSTANDARD=LVCMOS25; # Bank
LOC = W21 | IOSTANDARD=LVCMOS25; # Bank
LOC = W22 | IOSTANDARD=LVCMOS25; # Bank
LOC = W19 | IOSTANDARD=LVCMOS25; # Bank
LOC = M19 | IOSTANDARD=LVCMOS25; # Bank
LOC = J23 | IOSTANDARD=LVCMOS25; # Bank
LOC = J24 | IOSTANDARD=LVCMOS25; # Bank
LOC = L22 | IOSTANDARD=LVCMOS25; # Bank
LOC = L23 | IOSTANDARD=LVCMOS25; # Bank
LOC = K23 | IOSTANDARD=LVCMOS25; # Bank
LOC = K24 | IOSTANDARD=LVCMOS25; # Bank
LOC = L21 | IOSTANDARD=LVCMOS25; # Bank
LOC = K21 | IOSTANDARD=LVCMOS25; # Bank
LOC = J21 | IOSTANDARD=LVCMOS25; # Bank
LOC = J22 | IOSTANDARD=LVCMOS25; # Bank
LOC = M20 | IOSTANDARD=LVCMOS25; # Bank
LOC = L20 | IOSTANDARD=LVCMOS25; # Bank
LOC = J29 | IOSTANDARD=LVCMOS25; # Bank
LOC = H29 | IOSTANDARD=LVCMOS25; # Bank
LOC = J27 | IOSTANDARD=LVCMOS25; # Bank
LOC = J28 | IOSTANDARD=LVCMOS25; # Bank
LOC = L30 | IOSTANDARD=LVCMOS25; # Bank
LOC = K30 | IOSTANDARD=LVCMOS25; # Bank
LOC = K26 | IOSTANDARD=LVCMOS25; # Bank
LOC = J26 | IOSTANDARD=LVCMOS25; # Bank
LOC = L26 | IOSTANDARD=LVCMOS25; # Bank
LOC = L27 | IOSTANDARD=LVCMOS25; # Bank
LOC = L25 | IOSTANDARD=LVDS_25; # Bank
LOC = K25 | IOSTANDARD=LVDS_25; # Bank
LOC = K28 | IOSTANDARD=LVDS_25; # Bank
LOC = K29 | IOSTANDARD=LVDS_25; # Bank
LOC = M28 | IOSTANDARD=LVCMOS25; # Bank
LOC = L28 | IOSTANDARD=LVCMOS25; # Bank
LOC = M29 | IOSTANDARD=LVCMOS25; # Bank
LOC = M30 | IOSTANDARD=LVCMOS25; # Bank
LOC = N27 | IOSTANDARD=LVCMOS25; # Bank
LOC = M27 | IOSTANDARD=LVCMOS25; # Bank
LOC = N29 | IOSTANDARD=LVCMOS25; # Bank
LOC = N30 | IOSTANDARD=LVCMOS25; # Bank
LOC = N25 | IOSTANDARD=LVCMOS25; # Bank
LOC = N26 | IOSTANDARD=LVCMOS25; # Bank
LOC = N19 | IOSTANDARD=LVCMOS25; # Bank
LOC = N20 | IOSTANDARD=LVCMOS25; # Bank
LOC = N21 | IOSTANDARD=LVCMOS25; # Bank
LOC = N22 | IOSTANDARD=LVCMOS25; # Bank
LOC = P23 | IOSTANDARD=LVCMOS25; # Bank
LOC = N24 | IOSTANDARD=LVCMOS25; # Bank
LOC = P21 | IOSTANDARD=LVCMOS25; # Bank
LOC = P22 | IOSTANDARD=LVCMOS25; # Bank
LOC = M24 | IOSTANDARD=LVCMOS25; # Bank
LOC = M25 | IOSTANDARD=LVCMOS25; # Bank
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KC705 Board UCF Listing
14 VCCO - VCC2V5_FPGA - IO_L8N_T1_D12_14
14 VCCO - VCC2V5_FPGA - IO_L9P_T1_DQS_14
14 VCCO - VCC2V5_FPGA - IO_L9N_T1_DQS_D13_14
14 VCCO - VCC2V5_FPGA - IO_L10P_T1_D14_14
14 VCCO - VCC2V5_FPGA - IO_L10N_T1_D15_14
14 VCCO - VCC2V5_FPGA - IO_L11P_T1_SRCC_14
14 VCCO - VCC2V5_FPGA - IO_L11N_T1_SRCC_14
14 VCCO - VCC2V5_FPGA - IO_L12P_T1_MRCC_14
14 VCCO - VCC2V5_FPGA - IO_L12N_T1_MRCC_14
14 VCCO - VCC2V5_FPGA - IO_L13P_T2_MRCC_14
14 VCCO - VCC2V5_FPGA - IO_L13N_T2_MRCC_14
14 VCCO - VCC2V5_FPGA - IO_L14P_T2_SRCC_14
14 VCCO - VCC2V5_FPGA - IO_L14N_T2_SRCC_14
14 VCCO - VCC2V5_FPGA - IO_L15P_T2_DQS_RDWR_B_14
14 VCCO - VCC2V5_FPGA - IO_L15N_T2_DQS_DOUT_CSO_B_14
14 VCCO - VCC2V5_FPGA - IO_L16P_T2_CSI_B_14
14 VCCO - VCC2V5_FPGA - IO_L16N_T2_A15_D31_14
14 VCCO - VCC2V5_FPGA - IO_L17P_T2_A14_D30_14
14 VCCO - VCC2V5_FPGA - IO_L17N_T2_A13_D29_14
14 VCCO - VCC2V5_FPGA - IO_L18P_T2_A12_D28_14
14 VCCO - VCC2V5_FPGA - IO_L18N_T2_A11_D27_14
14 VCCO - VCC2V5_FPGA - IO_L19P_T3_A10_D26_14
14 VCCO - VCC2V5_FPGA - IO_L19N_T3_A09_D25_VREF_14
14 VCCO - VCC2V5_FPGA - IO_L20P_T3_A08_D24_14
14 VCCO - VCC2V5_FPGA - IO_L20N_T3_A07_D23_14
14 VCCO - VCC2V5_FPGA - IO_L21P_T3_DQS_14
14 VCCO - VCC2V5_FPGA - IO_L21N_T3_DQS_A06_D22_14
14 VCCO - VCC2V5_FPGA - IO_L22P_T3_A05_D21_14
14 VCCO - VCC2V5_FPGA - IO_L22N_T3_A04_D20_14
14 VCCO - VCC2V5_FPGA - IO_L23P_T3_A03_D19_14
14 VCCO - VCC2V5_FPGA - IO_L23N_T3_A02_D18_14
14 VCCO - VCC2V5_FPGA - IO_L24P_T3_A01_D17_14
14 VCCO - VCC2V5_FPGA - IO_L24N_T3_A00_D16_14
14 VCCO - VCC2V5_FPGA - IO_25_14
15 VCCO - VCC2V5_FPGA - IO_0_15
15 VCCO - VCC2V5_FPGA - IO_L1P_T0_AD0P_15
15 VCCO - VCC2V5_FPGA - IO_L1N_T0_AD0N_15
15 VCCO - VCC2V5_FPGA - IO_L2P_T0_AD8P_15
15 VCCO - VCC2V5_FPGA - IO_L2N_T0_AD8N_15
15 VCCO - VCC2V5_FPGA - IO_L3P_T0_DQS_AD1P_15
15 VCCO - VCC2V5_FPGA - IO_L3N_T0_DQS_AD1N_15
15 VCCO - VCC2V5_FPGA - IO_L4P_T0_AD9P_15
15 VCCO - VCC2V5_FPGA - IO_L4N_T0_AD9N_15
15 VCCO - VCC2V5_FPGA - IO_L5P_T0_AD2P_15
15 VCCO - VCC2V5_FPGA - IO_L5N_T0_AD2N_15
15 VCCO - VCC2V5_FPGA - IO_L6P_T0_15
15 VCCO - VCC2V5_FPGA - IO_L6N_T0_VREF_15
15 VCCO - VCC2V5_FPGA - IO_L7P_T1_AD10P_15
15 VCCO - VCC2V5_FPGA - IO_L7N_T1_AD10N_15
15 VCCO - VCC2V5_FPGA - IO_L8P_T1_AD3P_15
15 VCCO - VCC2V5_FPGA - IO_L8N_T1_AD3N_15
15 VCCO - VCC2V5_FPGA - IO_L9P_T1_DQS_AD11P_15
15 VCCO - VCC2V5_FPGA - IO_L9N_T1_DQS_AD11N_15
15 VCCO - VCC2V5_FPGA - IO_L10P_T1_AD4P_15
15 VCCO - VCC2V5_FPGA - IO_L10N_T1_AD4N_15
15 VCCO - VCC2V5_FPGA - IO_L11P_T1_SRCC_AD12P_15
15 VCCO - VCC2V5_FPGA - IO_L11N_T1_SRCC_AD12N_15
15 VCCO - VCC2V5_FPGA - IO_L12P_T1_MRCC_AD5P_15
15 VCCO - VCC2V5_FPGA - IO_L12N_T1_MRCC_AD5N_15
15 VCCO - VCC2V5_FPGA - IO_L13P_T2_MRCC_15
15 VCCO - VCC2V5_FPGA - IO_L13N_T2_MRCC_15
15 VCCO - VCC2V5_FPGA - IO_L14P_T2_SRCC_15
15 VCCO - VCC2V5_FPGA - IO_L14N_T2_SRCC_15
15 VCCO - VCC2V5_FPGA - IO_L15P_T2_DQS_15
15 VCCO - VCC2V5_FPGA - IO_L15N_T2_DQS_ADV_B_15
15 VCCO - VCC2V5_FPGA - IO_L16P_T2_A28_15
15 VCCO - VCC2V5_FPGA - IO_L16N_T2_A27_15
15 VCCO - VCC2V5_FPGA - IO_L17P_T2_A26_15
15 VCCO - VCC2V5_FPGA - IO_L17N_T2_A25_15
15 VCCO - VCC2V5_FPGA - IO_L18P_T2_A24_15
15 VCCO - VCC2V5_FPGA - IO_L18N_T2_A23_15
15 VCCO - VCC2V5_FPGA - IO_L19P_T3_A22_15
15 VCCO - VCC2V5_FPGA - IO_L19N_T3_A21_VREF_15
15 VCCO - VCC2V5_FPGA - IO_L20P_T3_A20_15
15 VCCO - VCC2V5_FPGA - IO_L20N_T3_A19_15
15 VCCO - VCC2V5_FPGA - IO_L21P_T3_DQS_15
15 VCCO - VCC2V5_FPGA - IO_L21N_T3_DQS_A18_15
15 VCCO - VCC2V5_FPGA - IO_L22P_T3_A17_15
15 VCCO - VCC2V5_FPGA - IO_L22N_T3_A16_15
15 VCCO - VCC2V5_FPGA - IO_L23P_T3_FOE_B_15
15 VCCO - VCC2V5_FPGA - IO_L23N_T3_FWE_B_15
77