Xilinx KC705 User Manual page 80

Appendix C: Master UCF Listing
NET DDR3_D28
NET DDR3_D25
NET DDR3_DM3
NET DDR3_D21
NET DDR3_D17
NET DDR3_D16
NET DDR3_D20
NET DDR3_DQS2_P
NET DDR3_DQS2_N
NET DDR3_D23
NET DDR3_D22
NET DDR3_D19
NET DDR3_D18
NET DDR3_DM2
NET PMBUS_CLK_LS
NET DDR3_D15
NET DDR3_D14
NET DDR3_D11
NET DDR3_D9
NET DDR3_DQS1_P
NET DDR3_DQS1_N
NET DDR3_D12
NET DDR3_D13
NET DDR3_D8
NET DDR3_D10
NET DDR3_DM1
NET DDR3_D6
NET DDR3_D0
NET DDR3_D5
NET DDR3_DQS0_P
NET DDR3_DQS0_N
NET DDR3_D2
NET DDR3_D3
NET DDR3_D4
NET DDR3_D1
NET DDR3_DM0
NET DDR3_D7
NET PMBUS_ALERT_LS
NET VRN_33
NET GPIO_SW_N
NET GPIO_SW_S
NET GPIO_LED_1_LS
NET GPIO_LED_0_LS
NET GPIO_LED_3_LS
NET GPIO_LED_2_LS
NET LCD_RS_LS
NET LCD_DB7_LS
NET LCD_DB6_LS
NET LCD_DB5_LS
NET LCD_DB4_LS
NET LCD_RW_LS
NET LCD_E_LS
NET DDR3_ODT1
NET DDR3_ODT0
NET DDR3_S1_B
NET DDR3_S0_B
NET DDR3_CAS_B
NET DDR3_RAS_B
NET DDR3_WE_B
NET DDR3_CLK1_P
NET DDR3_CLK1_N
NET SYSCLK_P
NET SYSCLK_N
NET DDR3_CLK0_P
NET DDR3_CLK0_N
NET DDR3_CKE1
NET DDR3_CKE0
NET DDR3_TEMP_EVENT
NET DDR3_BA2
NET DDR3_BA1
NET DDR3_BA0
NET DDR3_A15
NET DDR3_A14
NET DDR3_A13
NET DDR3_A12
NET DDR3_A11
NET DDR3_A10
NET DDR3_A9
NET DDR3_A8
NET DDR3_A7
NET DDR3_A6
80
LOC = AH17 | IOSTANDARD=SSTL15; # Bank
LOC = AJ17 | IOSTANDARD=SSTL15; # Bank
LOC = AE16 | IOSTANDARD=SSTL15; # Bank
LOC = AJ19 | IOSTANDARD=SSTL15; # Bank
LOC = AK19 | IOSTANDARD=SSTL15; # Bank
LOC = AG19 | IOSTANDARD=SSTL15; # Bank
LOC = AH19 | IOSTANDARD=SSTL15; # Bank
LOC = AJ18 | IOSTANDARD=SSTL15; # Bank
LOC = AK18 | IOSTANDARD=SSTL15; # Bank
LOC = AD19 | IOSTANDARD=SSTL15; # Bank
LOC = AE19 | IOSTANDARD=SSTL15; # Bank
LOC = AF18 | IOSTANDARD=SSTL15; # Bank
LOC = AG18 | IOSTANDARD=SSTL15; # Bank
LOC = AF17 | IOSTANDARD=SSTL15; # Bank
LOC = AG17 | IOSTANDARD=LVCMOS15; # Bank
LOC = AD18 | IOSTANDARD=SSTL15; # Bank
LOC = AE18 | IOSTANDARD=SSTL15; # Bank
LOC = AD17 | IOSTANDARD=SSTL15; # Bank
LOC = AD16 | IOSTANDARD=SSTL15; # Bank
LOC = Y19 | IOSTANDARD=DIFF_SSTL15; # Bank
LOC = Y18 | IOSTANDARD=DIFF_SSTL15; # Bank
LOC = AA18 | IOSTANDARD=SSTL15; # Bank
LOC = AB18 | IOSTANDARD=SSTL15; # Bank
LOC = AB19 | IOSTANDARD=SSTL15; # Bank
LOC = AC19 | IOSTANDARD=SSTL15; # Bank
LOC = AB17 | IOSTANDARD=SSTL15; # Bank
LOC = AE15 | IOSTANDARD=SSTL15; # Bank
LOC = AA15 | IOSTANDARD=SSTL15; # Bank
LOC = AB15 | IOSTANDARD=SSTL15; # Bank
LOC = AC16 | IOSTANDARD=DIFF_SSTL15; # Bank
LOC = AC15 | IOSTANDARD=DIFF_SSTL15; # Bank
LOC = AC14 | IOSTANDARD=SSTL15; # Bank
LOC = AD14 | IOSTANDARD=SSTL15; # Bank
LOC = AA17 | IOSTANDARD=SSTL15; # Bank
LOC = AA16 | IOSTANDARD=SSTL15; # Bank
LOC = Y16 | IOSTANDARD=SSTL15; # Bank
LOC = Y15 | IOSTANDARD=SSTL15; # Bank
LOC = AB14 | IOSTANDARD=LVCMOS15; # Bank
LOC = Y13 | IOSTANDARD=SSTL15; # Bank
LOC = AA12 | IOSTANDARD=LVCMOS15; # Bank
LOC = AB12 | IOSTANDARD=LVCMOS15; # Bank
LOC = AA8 | IOSTANDARD=LVCMOS15; # Bank
LOC = AB8 | IOSTANDARD=LVCMOS15; # Bank
LOC = AB9 | IOSTANDARD=LVCMOS15; # Bank
LOC = AC9 | IOSTANDARD=LVCMOS15; # Bank
LOC = Y11 | IOSTANDARD=LVCMOS15; # Bank
LOC = Y10 | IOSTANDARD=LVCMOS15; # Bank
LOC = AA11 | IOSTANDARD=LVCMOS15; # Bank
LOC = AA10 | IOSTANDARD=LVCMOS15; # Bank
LOC = AA13 | IOSTANDARD=LVCMOS15; # Bank
LOC = AB13 | IOSTANDARD=LVCMOS15; # Bank
LOC = AB10 | IOSTANDARD=LVCMOS15; # Bank
LOC = AC10 | IOSTANDARD=SSTL15; # Bank
LOC = AD8 | IOSTANDARD=SSTL15; # Bank
LOC = AE8 | IOSTANDARD=SSTL15; # Bank
LOC = AC12 | IOSTANDARD=SSTL15; # Bank
LOC = AC11 | IOSTANDARD=SSTL15; # Bank
LOC = AD9 | IOSTANDARD=SSTL15; # Bank
LOC = AE9 | IOSTANDARD=SSTL15; # Bank
LOC = AE11 | IOSTANDARD=DIFF_SSTL15; # Bank
LOC = AF11 | IOSTANDARD=DIFF_SSTL15; # Bank
LOC = AD12 | IOSTANDARD=LVDS; # Bank
LOC = AD11 | IOSTANDARD=LVDS; # Bank
LOC = AG10 | IOSTANDARD=DIFF_SSTL15; # Bank
LOC = AH10 | IOSTANDARD=DIFF_SSTL15; # Bank
LOC = AE10 | IOSTANDARD=SSTL15; # Bank
LOC = AF10 | IOSTANDARD=SSTL15; # Bank
LOC = AJ9 | IOSTANDARD=SSTL15; # Bank
LOC = AK9 | IOSTANDARD=SSTL15; # Bank
LOC = AG9 | IOSTANDARD=SSTL15; # Bank
LOC = AH9 | IOSTANDARD=SSTL15; # Bank
LOC = AK11 | IOSTANDARD=SSTL15; # Bank
LOC = AK10 | IOSTANDARD=SSTL15; # Bank
LOC = AH11 | IOSTANDARD=SSTL15; # Bank
LOC = AJ11 | IOSTANDARD=SSTL15; # Bank
LOC = AE13 | IOSTANDARD=SSTL15; # Bank
LOC = AF13 | IOSTANDARD=SSTL15; # Bank
LOC = AK14 | IOSTANDARD=SSTL15; # Bank
LOC = AK13 | IOSTANDARD=SSTL15; # Bank
LOC = AH14 | IOSTANDARD=SSTL15; # Bank
LOC = AJ14 | IOSTANDARD=SSTL15; # Bank
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32 VCCO - VCC1V5_FPGA - IO_L5P_T0_32
32 VCCO - VCC1V5_FPGA - IO_L5N_T0_32
32 VCCO - VCC1V5_FPGA - IO_L6P_T0_32
32 VCCO - VCC1V5_FPGA - IO_L7P_T1_32
32 VCCO - VCC1V5_FPGA - IO_L7N_T1_32
32 VCCO - VCC1V5_FPGA - IO_L8P_T1_32
32 VCCO - VCC1V5_FPGA - IO_L8N_T1_32
32 VCCO - VCC1V5_FPGA - IO_L9P_T1_DQS_32
32 VCCO - VCC1V5_FPGA - IO_L9N_T1_DQS_32
32 VCCO - VCC1V5_FPGA - IO_L10P_T1_32
32 VCCO - VCC1V5_FPGA - IO_L10N_T1_32
32 VCCO - VCC1V5_FPGA - IO_L11P_T1_SRCC_32
32 VCCO - VCC1V5_FPGA - IO_L11N_T1_SRCC_32
32 VCCO - VCC1V5_FPGA - IO_L12P_T1_MRCC_32
32 VCCO - VCC1V5_FPGA - IO_L12N_T1_MRCC_32
32 VCCO - VCC1V5_FPGA - IO_L13P_T2_MRCC_32
32 VCCO - VCC1V5_FPGA - IO_L13N_T2_MRCC_32
32 VCCO - VCC1V5_FPGA - IO_L14P_T2_SRCC_32
32 VCCO - VCC1V5_FPGA - IO_L14N_T2_SRCC_32
32 VCCO - VCC1V5_FPGA - IO_L15P_T2_DQS_32
32 VCCO - VCC1V5_FPGA - IO_L15N_T2_DQS_32
32 VCCO - VCC1V5_FPGA - IO_L16P_T2_32
32 VCCO - VCC1V5_FPGA - IO_L16N_T2_32
32 VCCO - VCC1V5_FPGA - IO_L17P_T2_32
32 VCCO - VCC1V5_FPGA - IO_L17N_T2_32
32 VCCO - VCC1V5_FPGA - IO_L18P_T2_32
32 VCCO - VCC1V5_FPGA - IO_L19P_T3_32
32 VCCO - VCC1V5_FPGA - IO_L20P_T3_32
32 VCCO - VCC1V5_FPGA - IO_L20N_T3_32
32 VCCO - VCC1V5_FPGA - IO_L21P_T3_DQS_32
32 VCCO - VCC1V5_FPGA - IO_L21N_T3_DQS_32
32 VCCO - VCC1V5_FPGA - IO_L22P_T3_32
32 VCCO - VCC1V5_FPGA - IO_L22N_T3_32
32 VCCO - VCC1V5_FPGA - IO_L23P_T3_32
32 VCCO - VCC1V5_FPGA - IO_L23N_T3_32
32 VCCO - VCC1V5_FPGA - IO_L24P_T3_32
32 VCCO - VCC1V5_FPGA - IO_L24N_T3_32
32 VCCO - VCC1V5_FPGA - IO_25_VRP_32
33 VCCO - VCC1V5_FPGA - IO_0_VRN_33
33 VCCO - VCC1V5_FPGA - IO_L1P_T0_33
33 VCCO - VCC1V5_FPGA - IO_L1N_T0_33
33 VCCO - VCC1V5_FPGA - IO_L2P_T0_33
33 VCCO - VCC1V5_FPGA - IO_L2N_T0_33
33 VCCO - VCC1V5_FPGA - IO_L3P_T0_DQS_33
33 VCCO - VCC1V5_FPGA - IO_L3N_T0_DQS_33
33 VCCO - VCC1V5_FPGA - IO_L4P_T0_33
33 VCCO - VCC1V5_FPGA - IO_L4N_T0_33
33 VCCO - VCC1V5_FPGA - IO_L5P_T0_33
33 VCCO - VCC1V5_FPGA - IO_L5N_T0_33
33 VCCO - VCC1V5_FPGA - IO_L6P_T0_33
33 VCCO - VCC1V5_FPGA - IO_L6N_T0_VREF_33
33 VCCO - VCC1V5_FPGA - IO_L7P_T1_33
33 VCCO - VCC1V5_FPGA - IO_L7N_T1_33
33 VCCO - VCC1V5_FPGA - IO_L8P_T1_33
33 VCCO - VCC1V5_FPGA - IO_L8N_T1_33
33 VCCO - VCC1V5_FPGA - IO_L9P_T1_DQS_33
33 VCCO - VCC1V5_FPGA - IO_L9N_T1_DQS_33
33 VCCO - VCC1V5_FPGA - IO_L10P_T1_33
33 VCCO - VCC1V5_FPGA - IO_L10N_T1_33
33 VCCO - VCC1V5_FPGA - IO_L11P_T1_SRCC_33
33 VCCO - VCC1V5_FPGA - IO_L11N_T1_SRCC_33
33 VCCO - VCC1V5_FPGA - IO_L12P_T1_MRCC_33
33 VCCO - VCC1V5_FPGA - IO_L12N_T1_MRCC_33
33 VCCO - VCC1V5_FPGA - IO_L13P_T2_MRCC_33
33 VCCO - VCC1V5_FPGA - IO_L13N_T2_MRCC_33
33 VCCO - VCC1V5_FPGA - IO_L14P_T2_SRCC_33
33 VCCO - VCC1V5_FPGA - IO_L14N_T2_SRCC_33
33 VCCO - VCC1V5_FPGA - IO_L15P_T2_DQS_33
33 VCCO - VCC1V5_FPGA - IO_L15N_T2_DQS_33
33 VCCO - VCC1V5_FPGA - IO_L16P_T2_33
33 VCCO - VCC1V5_FPGA - IO_L16N_T2_33
33 VCCO - VCC1V5_FPGA - IO_L17P_T2_33
33 VCCO - VCC1V5_FPGA - IO_L17N_T2_33
33 VCCO - VCC1V5_FPGA - IO_L18P_T2_33
33 VCCO - VCC1V5_FPGA - IO_L18N_T2_33
33 VCCO - VCC1V5_FPGA - IO_L19P_T3_33
33 VCCO - VCC1V5_FPGA - IO_L19N_T3_VREF_33
33 VCCO - VCC1V5_FPGA - IO_L20P_T3_33
33 VCCO - VCC1V5_FPGA - IO_L20N_T3_33
33 VCCO - VCC1V5_FPGA - IO_L21P_T3_DQS_33
33 VCCO - VCC1V5_FPGA - IO_L21N_T3_DQS_33
UG810 (v1.3) May 10, 2013
KC705 Evaluation Board