Xilinx KC705 User Manual page 21

The KC705 board includes a secure digital input/output (SDIO) interface to provide
user-logic access to general purpose non-volatile SDIO memory cards and peripherals. The
SD card slot is designed to support 50 MHz high speed SD cards.
The SDIO signals are connected to I/O bank 12 which has its VCCO set to VADJ. A Texas
Instruments I TXB0108 8-bit bidirectional voltage-level translator is used between the
FPGA and the SD card connector (U9).
interface on the KC705 board.
X-Ref Target - Figure 1-7
SDIO_DAT0_LS
SDIO_DAT1_LS
SDIO_DAT2_LS
To FPGA
Bank 12 SDIO_CD_DAT3_LS
(U1)
SDIO_CMD_LS
SDIO_CLK_LS
Table 1-7
Table 1-7: SDIO Connections to the FPGA
U1 FPGA Pin
Schematic Net Name
Name
Y21 SDIO_SDWP
AA21 SDIO_SDDET
AB22 SDIO_CMD_LS
AB23 SDIO_CLK_LS
AA22 SDIO_DAT2_LS
AA23 SDIO_DAT1_LS
AC20 SDIO_DAT0_LS
AC21 SDIO_CD_DAT3_LS
KC705 Evaluation Board
UG810 (v1.3) May 10, 2013
VADJ
51.1K 1% Six Places
0.1μF 25V
U57
TXB0108
Voltage-Level
Translator
VCCA
A1
A2
A3
A4
A5
A6
NC
A7
NC
A8
OE
C543
0.1μF 25V
X5R
GND
Figure 1-7: SD card interface
lists the SD card interface connections to the FPGA.
U57 Level Shifter
Pin Name (A)
N/A
N/A
A5
A6
A3
A2
A1
A4
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Figure 1-7 shows the connections of the SD card
VCC3V3
VCC3V3
51.1K 1% Six Places
C22
X5R
GND
VCCB
B1
B2
B3
SDIO_CD_DAT3
B4
B5
B6
To FPGA
B7
Bank 12
B8
(U1)
GND
GND
VADJ
Pin Name (B)
N/A
N/A
B6
B7
B4
B3
B1
B5
Feature Descriptions
VCC3V3
C22
0.1μF 25V
X5R
GND
U9
SDIO Card
Connector
4
VDD
7
SDIO_DAT0
DAT0
8
SDIO_DAT1
DAT1
9
SDIO_DAT2
DAT2
1
CD_DAT3
2
SDIO_CMD
CMD
5
SDIO_CLK
CLK
10
SDIO_SDDET
DETECT
IOGND2
11
SDIO_SDWP
PROTECT
IOGND1
12
NC
D_P
GNDTAB4
GNDTAB3
3
VSS1 GNDTAB2
6
VSS2 GNDTAB1
GND
UG810_c1_06_120111
U9 SDIO Connector
Pin Number Pin Name
11 SDWP
10 SDDET
2 CMD
5
9 DAT2
8 DAT1
7 DAT0
1 CD_DAT3
18
17
16
15
14
13
GND
CLK
21