Xilinx KC705 User Manual page 60

Chapter 1: KC705 Evaluation Board Features
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Table 1-29: LPC Connections, J2 to FPGA U1
J2 Pin Net Name
C2 FMC_LPC_DP0_C2M_P
C3 FMC_LPC_DP0_C2M_N
C6 FMC_LPC_DP0_M2C_P
C7 FMC_LPC_DP0_M2C_N
C10 FMC_LPC_LA06_P
C11 FMC_LPC_LA06_N
C14 FMC_LPC_LA10_P
C15 FMC_LPC_LA10_N
C18 FMC_LPC_LA14_P
C19 FMC_LPC_LA14_N
C22 FMC_LPC_LA18_CC_P
C23 FMC_LPC_LA18_CC_N
C26 FMC_LPC_LA27_P
C27 FMC_LPC_LA27_N
C30 FMC_LPC_IIC_SCL
C31 FMC_LPC_IIC_SDA
C34 GND
C35 VCC12_P
C37 VCC12_P
C39 VCC3V3
G2 FMC_LPC_CLK1_M2C_P
G3 FMC_LPC_CLK1_M2C_N
60
1 GTX transceiver
1 GTX clock
2 differential clocks
61 ground and 9 power connections
FPGA U1
Pin
F2
F1
F6
F5
AK20
AK21
AJ24
AK25
AD21
AK21
AD27
AD28
AJ28
AJ29
AG29
AH29
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J2 Pin Net Name
D1 PWRCTL1_VCC4A_PG
D4 FMC_LPC_GBTCLK0_M2C_P
D5 FMC_LPC_GBTCLK0_M2C_N
D8 FMC_LPC_LA01_CC_P
D9 FMC_LPC_LA01_CC_N
D11 FMC_LPC_LA05_P
D12 FMC_LPC_LA05_N
D14 FMC_LPC_LA09_P
D15 FMC_LPC_LA09_N
D17 FMC_LPC_LA13_P
D18 FMC_LPC_LA13_N
D20 FMC_LPC_LA17_CC_P
D21 FMC_LPC_LA17_CC_N
D23 FMC_LPC_LA23_P
D24 FMC_LPC_LA23_N
D26 FMC_LPC_LA26_P
D27 FMC_LPC_LA26_N
D29 FMC_LPC_TCK_BUF
D30 FMC_HPC_TDO_LPC_TDI
D31 FMC_LPC_TDO_FPGA_TDI
D32 VCC3V3
D33 FMC_LPC_TMS_BUF
D34 NC
D35 GND
D36 VCC3V3
D38 VCC3V3
D40 VCC3V3
H1 NC
H2 FMC_LPC_PRSNT_M2C_B
FPGA U1
Pin
N8
N7
AE23
AF23
AG22
AH22
AK23
AK24
AB24
AC25
AB27
AC27
AH26
AH27
AK29
AK30
KC705 Evaluation Board
UG810 (v1.3) May 10, 2013