Xilinx KC705 User Manual page 25

X-Ref Target - Figure 1-10
For more about the Si Time SiT9102 see
Programmable User Clock Source
[Figure
The KC705 board has a programmable low-jitter 3.3V differential oscillator (U45) the
FPGA MRCC inputs of bank 15. This USER_CLOCK_P and USER_CLOCK_N clock signal
pair are connected to FPGA U1 pins K28 and K29 respectively. On power-up the user clock
defaults to an output frequency of 156.250 MHz. User applications can change the output
frequency within the range of 10 MHz to 810 MHz through an I
the KC705 board will revert the user clock to its default frequency of 156.250 MHz.
•
•
•
The user clock circuit is shown in
X-Ref Target - Figure 1-11
For more information about the Silicon Labs Si570 see
KC705 Evaluation Board
UG810 (v1.3) May 10, 2013
C550
0.1 μF 10V
X5R
GND
Figure 1-10: System Clock Source
1-2, callout 8]
Programmable Oscillator: Silicon Labs Si570BAB0000544DG (10 MHz - 810 MHz)
Differential Output
2
I C address 0x5D
VCC3V3
R8
4.7KΩ 5%
USER CLOCK SDA
To I 2 C
Bus Switch
USER CLOCK SCL
(U49)
GND
Figure 1-11: User Clock Source
www.xilinx.com
VCC2V5
U6
SIT9102
200 MHz
Oscillator
1 6
OE VCC
2 5
NC OUT_B
3 4
GND OUT
[Ref 7].
Figure 1-11.
U45
Si570
Programmable
Oscillator
1 6
NC VDD
2
OE
7
USER CLOCK N
SDA 5
CLK-
8
4 USER CLOCK P
SCL CLK+
3
GND
[Ref
Feature Descriptions
SYSCLK_N
R459
100Ω 1%
SYSCLK_P
UG810_c1_09_120211
2
C interface. Power cycling
VCC3V3
C77
0.01 μF 25V
X7R
GND
10 MHz - 810 MHz
50 PPM
UG810_c1_10_011212
8].
25