Xilinx KC705 User Manual page 70

Chapter 1: KC705 Evaluation Board Features
FPGA over the 16-bit data path from the Linear BPI Flash memory at a maximum
synchronous read rate of 33 MHz. The bitstream stored in the Flash memory must be
generated with a bitgen option to divide the EMCCLK by two.
X-Ref Target - Figure 1-40
SW13
U58
P30 1Gb
Flash Memory
RST_B
CLK
WE_B
OE_B
ADV_B
CE_B
A[27:01]
D[15:00]
U7
N25Q128A13BSF-40F
QUAD SPI
D
Q
HOLD_B
W_B
C
S-B
70
SW14
GND
Mode
Switch
2.5 V
Part of
SW13
A[26:00]
U63
0
1
Boot Select
Demultiplexer
U64
Oscillator
66 MHz
Figure 1-40: KC705 Board Configuration Circuit
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U1
FPGA
PROG_B
M[2:0]
Bank 0
INIT_B
CCLK
FWE_B
FOE_B
ADV_B
Bank 15
RS1
RS0
A26
A25
GND
NC
A[26:25]
A[24:16]
A[15:00]
D[15:00]
Bank 14
FCS_B
EMCCLK
VCCAUXIO (2.0V)
VBATT
TCK
TMS
TDI
TDO
300 Ω
DONE
DS20
GREEN
27.4 Ω
GND
CSO_B
ETHERNET MDC
POUC_B
R405
1 kΩ
GND
UG810_c1_33_031612
KC705 Evaluation Board
UG810 (v1.3) May 10, 2013
D11
BAS40-04
5 kΩ
B1
GND