Xilinx KC705 User Manual page 37

Table 1-16: PHY Default Interface Mode
On power-up, or on reset, the PHY is configured to operate in GMII mode with PHY
address 0b00111 using the settings shown in
via software commands passed over the MDIO interface.
Table 1-17: Board Connections for PHY Configuration Pins
SGMII GTX Transceiver Clock Generator
[Figure
An Integrated Circuit Systems ICS844021I chip (U2) generates a high-quality, low-jitter,
125 MHz LVDS clock from a 25 MHz crystal (X3). This clock is sent to FPGA U1, bank 117
GTX transceiver (clock pins G8 (P) and G7 (N)) driving the SGMII interface. Series AC
coupling capacitors are present to allow the clock input of the FPGA to set the common
mode voltage.
KC705 Evaluation Board
UG810 (v1.3) May 10, 2013
Mode
GMII/MII to copper
(default)
SGMII to copper,
no clock
RGMII
Connection on
Pin
Board Definition and Value
CFG0 V 2.5V
CC
CFG1 Ground
CFG2 V 2.5V
CC
CFG3 V 2.5V
CC
CFG4 V 2.5V HWCFG_MD[2] = 1
CC
CFG5 V 2.5V
CC
CFG6 PHY_LED_RX
1-2, callout 16]
Figure 1-18
www.xilinx.com
Jumper Settings
J29
Jumper over pins 1-2 Jumper over pins 1-2
Jumper over pins 2-3 Jumper over pins 2-3
Jumper over pins 1-2
Table 1-17. These settings can be overwritten
Bit[2]
Definition and Value
PHYADR[2] = 1 PHYADR[1] = 1
ENA_PAUSE = 0 PHYADR[4] = 0
ANEG[3] = 1 ANEG[2] = 1
ANEG[0] = 1 ENA_XC = 1
HWCFG_MD[1] = 1
DIS_FC = 1 DIS_SLEEP = 1
SEL_BDT = 0 INT_POL = 1
shows the Ethernet SGMII clock source.
Feature Descriptions
J30 J64
No jumper
No jumper
No jumper Jumper on
Bit[1] Bit[0]
Definition and Value
PHYADR[0] = 1
PHYADR[3] = 0
ANEG[1] = 1
DIS_125 = 1
HWCFG_MD[0] = 1
HWCFG_MD[3] = 1
75/50Ω= 0
37