Xilinx KC705 User Manual page 64

Chapter 1: KC705 Evaluation Board Features
FMC_VADJ Voltage Control
The FMC_VADJ rail is set to 2.5V. When the KC705 board is powered on, the state of the
FMC_VADJ_ON_B signal wired to header J65 is sampled by the Texas Instruments
UCD9248 controller U55. If a jumper is installed on J65, signal FMC_VADJ_ON_B is held
low, and the TI controller U55 energizes the FMC_VADJ rail at power on.
Because the rail turn on decision is made at power on time based on the presence of the J65
jumper, removing the jumper at J65 after the board is powered up will not affect the 2.5V
power delivered to the FMC_VADJ rail and it will remain on.
A jumper installed at J65 is the default setting.
If a jumper is not installed on J65, signal FMC_VADJ_ON_B is high, and the KC705 board
will not energize the FMC_VADJ 2.5V at power on. In this mode the user can control when
to turn on FMC_VADJ and to what voltage level (1.8V - 3.3V). With FMC_VADJ off the
FPGA will still configure and has access to the TI controller PMBUS (on bank 32) along
with the FMC_VADJ_ON_B signal (on bank 15 pin J27). The combination of these allows
the user to develop code to command the FMC_VADJ rail to be set to something other than
the default setting of 2.5V. Once the new FMC_VADJ voltage level has been programmed
into TI controller U55, the FMC_VADJ_ON_B signal can be driven low by the user logic
and the FMC_VADJ rail will come up at the new FMC_VADJ voltage level. Installing a
jumper at J65 after a KC705 board powers up in this mode will turn on the FMC_VADJ rail.
For access to Texas Instruments fusion tools documentation describing PMBUS
programming for the UCD9248 digital power controller see
Cooling Fan Control
Cooling fan RPM is controlled and monitored by user-created IP in the FPGA using the fan
control circuit is shown in
FPGA U1 is cooled by a 12V DC fan connected to J61. 12V
J61 pin 2. The fan GND return is provided through J61 pin 1 and transistor Q17. Fan speed
is controlled by a pulse-width-modulated signal from FPGA U1 pin L26 (on bank 15)
driving the gate of Q17. The default unprogrammed FPGA fan operation mode is ON. The
fan speed tachometer signal on J61 pin 3 can be monitored on FPGA U1 pin U22 (on bank
14).
X-Ref Target - Figure 1-36
64
J61
3
Fan Tach
2
Cooling
Fan +12V
Fan
1
Fan GND
VCC2V5
SM_FAN_PWM
FPGA
U1 Pin L26
Figure 1-36: FPGA Cooling Fan Circuit
www.xilinx.com
Figure 1-36.
VCC12_P
R392 R393
10.0K 1% 10.0K 1%
1/10W 1/10W
D14
100V
500 mW
DL4148
2 4
R391
Q17
1.00K 1%
NDT30555L
1/16W
1
1.3 W
3
GND
[Ref 9].
is provided to the fan through
DC
SM_FAN_TACH
D15
R390
2.7V
4.75K 1%
500 mW
1/10W
MM3Z2V7B
GND
UG810_c1_101_031312
KC705 Evaluation Board
UG810 (v1.3) May 10, 2013
FPGA
U1 Pin U22