Xilinx KC705 User Manual page 10

Chapter 1: KC705 Evaluation Board Features
X-Ref Target - Figure 1-3
The default mode setting is M[2:0] = 010, which selects Master BPI at board power-on.
Refer to the
switch SW13.
Table 1-2: KC705 board FPGA Configuration Modes
For full details on configuring the FPGA, see UG470, 7 Series FPGAs Configuration User
Guide
Encryption Key Backup Circuit
FPGA U1 implements bitstream encryption key technology. The KC705 board provides the
encryption key backup battery circuit shown in
button-type battery B1 is soldered to the board with the positive output connected to
FPGA U1 VCCBATT pin C10. The battery supply current I
when board power is off. B1 is charged from the VCCAUX_IO 2.0V rail through a series
diode with a typical forward voltage drop of 0.38V. and 4.7 KΩ current limit resistor. The
nominal charging voltage is 1.62V.
10
ON Position = 1
Configuration Options, page 69
Configuration SW13 DIP switch
Mode Settings (M[2:0])
Master SPI
Master BPI
JTAG
www.xilinx.com
1 2 3 4 5
Figure 1-3: SW13 Default Settings
for detailed information about the mode
001
010
101
Figure
OFF Position = 0
UG810_c1_03_011112
Bus CCLK
Width Direction
x1, x2, x4 Output
x8, x16 Output
x1 Not Applicable
1-4. The rechargeable 1.5V lithium
specification is 150 nA max
BATT
KC705 Evaluation Board
UG810 (v1.3) May 10, 2013