Xilinx KC705 User Manual page 32

Chapter 1: KC705 Evaluation Board Features
Table 1-11: PCIe Edge Connector Connections (Cont'd)
Schematic FPGA Pin
Net Name (U1)
PCIE_TX1_P M2
PCIE_TX1_N M1
PCIE_TX2_P N4
PCIE_TX2_N N3
PCIE_TX3_P P2
PCIE_TX3_N P1
PCIE_TX4_P T2
PCIE_TX4_N T1
PCIE_TX5_P U4
PCIE_TX5_N U3
PCIE_TX6_P V2
PCIE_TX6_N V1
PCIE_TX7_P Y2
PCIE_TX7_N Y1
PCIE_CLK_QO_P
U8
PCIE_CLK_QO_N
U7
PCIE_PRSNT_B J32 2, 4, 6
PCIE_WAKE_B
F23
PCIE_PERST_B G25
Table 1-12
Table 1-12: GTX Quad 115 PCIe Edge Connector Connections
Quad 115
Pin Name
MGTXTXP0_115_Y2
MGTXTXN0_115_Y1
MGTXRXP0_115_AA4
MGTXRXN0_115_AA3
MGTXTXP1_115_V2
MGTXTXN1_115_V1
MGTXRXP1_115_Y6
MGTXRXN1_115_Y5
MGTXTXP2_115_U4
MGTXTXN2_115_U3
32
PCIe Edge PCIe Edge Pin
Connector Pin Name
A21 PERp1
A22 PERn1
A25 PERp2
A26 PERn2
A29 PERp3
A30 PERn3
A35 PERp4
A36 PERn4
A39 PERp5
A40 PERn5
A43 PERp6
A44 PERn6
A47 PERp7
A48 PERn7
A13 REFCLK+
A14 REFCLK-
A1 PRSNT#1
B11 WAKE#
A11 PERST
lists the PCIe edge connector connections for Quad 115.
FPGA Pin Schematic
(U1) Net Name
Y2 PCIE_TX7_P
Y1 PCIE_TX7_N
AA4 PCIE_RX7_P
AA3 PCIE_RX7_N
V2 PCIE_TX6_P
V1 PCIE_TX6_N
Y6 PCIE_RX6_P
Y5 PCIE_RX6_N
U4 PCIE_TX5_P
U3 PCIE_TX5_N
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Function
Integrated Endpoint block transmit pair
Integrated Endpoint block transmit pair
Integrated Endpoint block transmit pair
Integrated Endpoint block transmit pair
Integrated Endpoint block transmit pair
Integrated Endpoint block transmit pair
Integrated Endpoint block transmit pair
Integrated Endpoint block transmit pair
Integrated Endpoint block transmit pair
Integrated Endpoint block transmit pair
Integrated Endpoint block transmit pair
Integrated Endpoint block transmit pair
Integrated Endpoint block transmit pair
Integrated Endpoint block transmit pair
Integrated Endpoint block differential
clock pair from PCIe
Integrated Endpoint block differential
clock pair from PCIe
J42 Lane Size Select jumper
Integrated Endpoint block wake signal,
not connected on KC705 board
Integrated Endpoint block reset signal
PCIe Edge PCIe Edge
Connector Pin Pin Name
A47 PERp7
A48 PERn7
B45 PETp7
B46 PETn7
A43 PERp6
A44 PERn6
B41 PETp6
B42 PETn6
A39 PERp5
A40 PERn5
FFG900
Placement
GTXE2_CHANNEL_X0Y6
GTXE2_CHANNEL_X0Y6
GTXE2_CHANNEL_X0Y5
GTXE2_CHANNEL_X0Y5
GTXE2_CHANNEL_X0Y4
GTXE2_CHANNEL_X0Y4
GTXE2_CHANNEL_X0Y3
GTXE2_CHANNEL_X0Y3
GTXE2_CHANNEL_X0Y2
GTXE2_CHANNEL_X0Y2
GTXE2_CHANNEL_X0Y1
GTXE2_CHANNEL_X0Y1
GTXE2_CHANNEL_X0Y0
GTXE2_CHANNEL_X0Y0
MGT_BANK_115
MGT_BANK_115
NA
NA
NA
FFG900
Placement
GTXE2_CHANNEL_X0Y0
GTXE2_CHANNEL_X0Y0
GTXE2_CHANNEL_X0Y0
GTXE2_CHANNEL_X0Y0
GTXE2_CHANNEL_X0Y1
GTXE2_CHANNEL_X0Y1
GTXE2_CHANNEL_X0Y1
GTXE2_CHANNEL_X0Y1
GTXE2_CHANNEL_X0Y2
GTXE2_CHANNEL_X0Y2
KC705 Evaluation Board
UG810 (v1.3) May 10, 2013