Xilinx KC705 User Manual page 27

User SMA Clock Input
[Figure
An external high-precision clock signal can be provided to the FPGA bank 15 by
connecting differential clock signals through the onboard 50Ω SMA connectors J11 (P) and
J12 (N). The differential clock has signal names are USER_SMA_CLOCK_P and
USER_SMA_CLOCK_N, which are connected to FPGA U1 pins L25 and K25 respectively.
The user-provided 2.5 V differential clock circuit is shown in
X-Ref Target - Figure 1-12
GTX SMA Clock Input
[Figure
The KC705 board includes a pair of SMA connectors for a GTX clock wired to GTX Quad
bank 117. This differential clock has signal names SMA_MGT_REFCLK_P and
SMA_REFCLK_N, which are connected to FPGA U1 pins J8 and J7 respectively.
Figure 1-13
•
•
X-Ref Target - Figure 1-13
KC705 Evaluation Board
UG810 (v1.3) May 10, 2013
1-2, callout 9]
SMA
Connector
SMA
Connector
Figure 1-12: User SMA Clock Source
1-2, callout 10]
shows this AC-coupled clock circuit.
External user-provided GTX reference clock on SMA input connectors
Differential Input
J16
SMA_MGT_REFCLK_C_P
SMA
Connector
J15
GND
SMA_MGT_REFCLK_C_N
SMA
Connector
GND
Figure 1-13: GTX SMA Clock Source
www.xilinx.com
J11
USER_SMA_CLOCK_P
GND
J12
USER_SMA_CLOCK_N
GND
UG810_c1_11_072111
C11
SMA_MGT_REFCLK_P
0.01 μF 25V
X7R
C10
SMA_MGT_REFCLK_N
0.01 μF 25V
X7R
Feature Descriptions
Figure 1-12.
UG810_c1_12_072111
27