Xilinx KC705 User Manual page 18

Chapter 1: KC705 Evaluation Board Features
Table 1-5: BPI Flash Memory Connections to the FPGA (Cont'd)
Additional FPGA bitstreams can be stored and used for configuration by setting the Warm
Boot Start Address (WBSTAR) register contained in 7 series FPGAs. More information is
available in the reconfiguration and multiboot section in UG470, 7 Series FPGAs
Configuration User Guide. The configuration section in this document provides details on
the Master BPI configuration mode.
Figure 1-5
For more information about the Numonyx PC28F00AP30TF see
18
U1 FPGA Pin Net Name
T22 FLASH_D6
T23 FLASH_D7
U20 FLASH_D8
P29 FLASH_D9
R29 FLASH_D10
P27 FLASH_D11
P28 FLASH_D12
T30 FLASH_D13
P26 FLASH_D14
R26 FLASH_D15
U29 FLASH_WAIT
M25 FPGA_FWE_B
M24 FLASH_OE_B
B10 FPGA_CCLK
U63.6 FLASH_CE_B
M30 FLASH_ADV_B
A10 FPGA_INIT_B
shows the connections of the linear BPI Flash memory on the KC705 board.
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U58 BPI Flash Memory
Pin Number Pin Name
G6 DQ6
H7 DQ7
E1 DQ8
E3 DQ9
F3 DQ10
F4 DQ11
F5 DQ12
H5 DQ13
G7 DQ14
E7 DQ15
F7 WAIT
G8 WE_B
F8 OE_B
E6 CLK
B4 CE_B
F6 ADV_B
D4 RST_B
[Ref 5].
KC705 Evaluation Board
UG810 (v1.3) May 10, 2013