Xilinx KC705 User Manual page 24

Chapter 1: KC705 Evaluation Board Features
Table 1-8: KC705 Board Clock Sources (Cont'd)
Table 1-9
Table 1-9: Source to FPGA Clock Connections
System Clock Source
[Figure
The KC705 board has a 2.5V LVDS differential 200 MHz oscillator (U6) soldered onto the
back side of the board and wired to an FPGA MRCC clock input on bank 33. This 200 MHz
signal pair is named SYSCLK_P and SYSCLK_N, which are connected to FPGA U1 pins
AD12 and AD11 respectively.
•
•
•
The system clock circuit is shown in
24
Clock Name Reference
User SMA Clock
(differential pair)
GTX SMA REF Clock
(differential pair)
Jitter Attenuated Clock
lists the pin-to-pin connections from each clock source to the FPGA.
Clock Source Pin
U6.5
U6.4
U45.5 USER_CLOCK_N
U45.4
J12.1 USER_SMA_CLOCK_N
J11.1 USER_SMA_CLOCK_P
J15.1 SMA_MGT_REFCLK_N
J16.1 SMA_MGT_REFCLK_P
U70.29
U70.28
1-2, callout 7]
Oscillator: Si Time SiT9102AI-243N25E200.00000 (200 MHz)
PPM frequency jitter: 50 ppm
Differential Output
www.xilinx.com
USER_SMA_CLOCK_P (net name).
J11
See User SMA Clock Input, page
USER_SMA_CLOCK_N (net name)
J12
See User SMA Clock Input, page 27
SMA_MGT_REFCLK_P (net name).
J16
See GTX SMA Clock Input, page
SMA_MGT_REFCLK_N (net name).
J15
See GTX SMA Clock Input, page
Si5324C LVDS precision clock multiplier/jitter
U70 attenuator (Silicon Labs).
See Jitter Attenuated Clock, page
Net Name
SYSCLK_N
SYSCLK_P
USER_CLOCK_P
Si5326_OUT_N
Si5326_OUT_P
Figure 1-10.
Description
27.
27.
27.
28.
FPGA (U1) Pin
AD11
AD12
K29
K28
K25
L25
J7
J8
L7
L8
KC705 Evaluation Board
UG810 (v1.3) May 10, 2013