Xilinx KC705 User Manual page 15

Table 1-4: DDR3 Memory Connections to the FPGA (Cont'd)
KC705 Evaluation Board
UG810 (v1.3) May 10, 2013
U1 FPGA Pin Net Name
AB17 DDR3_DM1
AF17 DDR3_DM2
AE16 DDR3_DM3
AK5 DDR3_DM4
AJ3 DDR3_DM5
AF6 DDR3_DM6
AC7 DDR3_DM7
AC15 DDR3_DQS0_N
AC16 DDR3_DQS0_P
Y18 DDR3_DQS1_N
Y19 DDR3_DQS1_P
AK18 DDR3_DQS2_N
AJ18 DDR3_DQS2_P
AJ16 DDR3_DQS3_N
AH16 DDR3_DQS3_P
AJ7 DDR3_DQS4_N
AH7 DDR3_DQS4_P
AH1 DDR3_DQS5_N
AG2 DDR3_DQS5_P
AG3 DDR3_DQS6_N
AG4 DDR3_DQS6_P
AD1 DDR3_DQS7_N
AD2 DDR3_DQS7_P
AD8 DDR3_ODT0
AC10 DDR3_ODT1
AK3 DDR3_RESET_B
AC12 DDR3_S0_B
AE8 DDR3_S1_B
AJ9 DDR3_TEMP_EVENT
AE9 DDR3_WE_B
AC11 DDR3_CAS_B
AD9 DDR3_RAS_B
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Feature Descriptions
J1 DDR3 Memory
Pin Number Pin Name
28 DM1
46 DM2
63 DM3
136 DM4
153 DM5
170 DM6
187 DM7
10 DQS0_N
12 DQS0_P
27 DQS1_N
29 DQS1_P
45 DQS2_N
47 DQS2_P
62 DQS3_N
64 DQS3_P
135 DQS4_N
137 DQS4_P
152 DQS5_N
154 DQS5_P
169 DQS6_N
171 DQS6_P
186 DQS7_N
188 DQS7_P
116 ODT0
120 ODT1
30 RESET_B
114 S0_B
121 S1_B
198 EVENT_B
113 WE_B
115 CAS_B
110 RAS_B
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