Xilinx KC705 User Manual page 68

Chapter 1: KC705 Evaluation Board Features
X-Ref Target - Figure 1-38
XADC_VCC5V0
VADJ
Table 1-34
Table 1-34: XADC Header J46 Pinout
Net Name
VN, VP
XADC_VAUX0P, N
XADC_VAUX8N, P
DXP, DXN
XADC_AGND
XADC_VREF
XADC_VCC5V0
XADC_VCC_HEADER
VADJ
GND
XADC_GPIO_3, 2, 1, 0
68
XADC_VN
XADC_VAUX0P
XADC_VAUX8N
XADC_DXP
XADC_VREF
XADC_GPIO_1
XADC_GPIO_3
Figure 1-38: XADC header (J46)
describes the XADC header J46 pin functions.
J46 Pin
Number
1, 2 Dedicated analog input channel for the XADC.
Auxiliary analog input channel 0. Also supports use as IO inputs when anti
3, 6
alias capacitor is not present.
Auxiliary analog input channel 8. Also supports use as IO inputs when anti
7, 8
alias capacitor is not present.
9, 12 Access to thermal diode.
4, 5, 10 Analog ground reference.
11 1.25V reference from the board.
13 Filtered 5V supply from board.
14 Analog 1.8V supply for XADC.
15 VCCO supply for bank which is the source of DIO pins.
16 Digital Ground (board) Reference
Digital IO. These pins should come from the same bank. These IOs should not
19, 20, 17, 18 be shared with other functions because they are required to support three-state
operation.
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J46
1 2
3 4
5 6 XADC_VAUX0N
XADC_VAUX8P
7 8
9 10
11 12
XADC_VCC_HEADER
13 14
15 16
17 18 XADC_GPIO_0
XADC_GPIO_2
19 20
GND
XADC_AGND XADC_AGND
Description
XADC_VP
XADC_DXN
UG810_c1_31_121311
KC705 Evaluation Board
UG810 (v1.3) May 10, 2013