Xilinx KC705 User Manual page 78

Appendix C: Master UCF Listing
NET FLASH_A25
NET FLASH_A24
NET SFP_LOS_LS
NET PCIE_WAKE_B_LS
NET HDMI_R_D0
NET HDMI_R_D1
NET HDMI_R_D2
NET HDMI_R_D3
NET HDMI_R_D4
NET HDMI_R_D5
NET HDMI_R_D6
NET HDMI_R_D7
NET HDMI_R_D8
NET HDMI_R_D9
NET HDMI_R_D10
NET HDMI_R_D11
NET FMC_HPC_LA16_P
NET FMC_HPC_LA16_N
NET FMC_HPC_LA15_P
NET FMC_HPC_LA15_N
NET FMC_HPC_LA14_P
NET FMC_HPC_LA14_N
NET FMC_HPC_LA13_P
NET FMC_HPC_LA13_N
NET FMC_HPC_LA01_CC_P
NET FMC_HPC_LA01_CC_N
NET FMC_HPC_LA00_CC_P
NET FMC_HPC_LA00_CC_N
NET FMC_HPC_CLK0_M2C_P
NET FMC_HPC_CLK0_M2C_N
NET FMC_HPC_LA07_P
NET FMC_HPC_LA07_N
NET FMC_HPC_LA12_P
NET FMC_HPC_LA12_N
NET FMC_HPC_LA10_P
NET FMC_HPC_LA10_N
NET FMC_HPC_LA09_P
NET FMC_HPC_LA09_N
NET FMC_HPC_LA08_P
NET FMC_HPC_LA08_N
NET FMC_HPC_LA02_P
NET FMC_HPC_LA02_N
NET FMC_HPC_LA04_P
NET FMC_HPC_LA04_N
NET FMC_HPC_LA11_P
NET FMC_HPC_LA11_N
NET FMC_HPC_LA05_P
NET FMC_HPC_LA05_N
NET FMC_HPC_LA03_P
NET FMC_HPC_LA03_N
NET FMC_HPC_LA06_P
NET FMC_HPC_LA06_N
NET PCIE_PERST_LS
NET GPIO_LED_5_LS
NET HDMI_R_CLK
NET HDMI_R_HSYNC
NET HDMI_R_VSYNC
NET HDMI_SPDIF_OUT_LS
NET HDMI_R_SPDIF
NET HDMI_R_DE
NET HDMI_R_D12
NET HDMI_R_D13
NET HDMI_R_D14
NET HDMI_R_D15
NET HDMI_R_D16
NET HDMI_R_D17
NET FMC_HPC_LA33_P
NET FMC_HPC_LA33_N
NET FMC_HPC_LA32_P
NET FMC_HPC_LA32_N
NET FMC_HPC_LA31_P
NET FMC_HPC_LA31_N
NET FMC_HPC_LA30_P
NET FMC_HPC_LA30_N
NET FMC_HPC_LA18_CC_P
NET FMC_HPC_LA18_CC_N
NET FMC_HPC_LA17_CC_P
NET FMC_HPC_LA17_CC_N
NET FMC_HPC_CLK1_M2C_P
NET FMC_HPC_CLK1_M2C_N
NET FMC_HPC_LA20_P
78
LOC = M22 | IOSTANDARD=LVCMOS25; # Bank
LOC = M23 | IOSTANDARD=LVCMOS25; # Bank
LOC = P19 | IOSTANDARD=LVCMOS25; # Bank
LOC = F23 | IOSTANDARD=LVCMOS25; # Bank
LOC = B23 | IOSTANDARD=LVCMOS25; # Bank
LOC = A23 | IOSTANDARD=LVCMOS25; # Bank
LOC = E23 | IOSTANDARD=LVCMOS25; # Bank
LOC = D23 | IOSTANDARD=LVCMOS25; # Bank
LOC = F25 | IOSTANDARD=LVCMOS25; # Bank
LOC = E25 | IOSTANDARD=LVCMOS25; # Bank
LOC = E24 | IOSTANDARD=LVCMOS25; # Bank
LOC = D24 | IOSTANDARD=LVCMOS25; # Bank
LOC = F26 | IOSTANDARD=LVCMOS25; # Bank
LOC = E26 | IOSTANDARD=LVCMOS25; # Bank
LOC = G23 | IOSTANDARD=LVCMOS25; # Bank
LOC = G24 | IOSTANDARD=LVCMOS25; # Bank
LOC = B27 | IOSTANDARD=LVCMOS25; # Bank
LOC = A27 | IOSTANDARD=LVCMOS25; # Bank
LOC = C24 | IOSTANDARD=LVCMOS25; # Bank
LOC = B24 | IOSTANDARD=LVCMOS25; # Bank
LOC = B28 | IOSTANDARD=LVCMOS25; # Bank
LOC = A28 | IOSTANDARD=LVCMOS25; # Bank
LOC = A25 | IOSTANDARD=LVCMOS25; # Bank
LOC = A26 | IOSTANDARD=LVCMOS25; # Bank
LOC = D26 | IOSTANDARD=LVCMOS25; # Bank
LOC = C26 | IOSTANDARD=LVCMOS25; # Bank
LOC = C25 | IOSTANDARD=LVCMOS25; # Bank
LOC = B25 | IOSTANDARD=LVCMOS25; # Bank
LOC = D27 | IOSTANDARD=LVCMOS25; # Bank
LOC = C27 | IOSTANDARD=LVCMOS25; # Bank
LOC = E28 | IOSTANDARD=LVCMOS25; # Bank
LOC = D28 | IOSTANDARD=LVCMOS25; # Bank
LOC = C29 | IOSTANDARD=LVCMOS25; # Bank
LOC = B29 | IOSTANDARD=LVCMOS25; # Bank
LOC = D29 | IOSTANDARD=LVCMOS25; # Bank
LOC = C30 | IOSTANDARD=LVCMOS25; # Bank
LOC = B30 | IOSTANDARD=LVCMOS25; # Bank
LOC = A30 | IOSTANDARD=LVCMOS25; # Bank
LOC = E29 | IOSTANDARD=LVCMOS25; # Bank
LOC = E30 | IOSTANDARD=LVCMOS25; # Bank
LOC = H24 | IOSTANDARD=LVCMOS25; # Bank
LOC = H25 | IOSTANDARD=LVCMOS25; # Bank
LOC = G28 | IOSTANDARD=LVCMOS25; # Bank
LOC = F28 | IOSTANDARD=LVCMOS25; # Bank
LOC = G27 | IOSTANDARD=LVCMOS25; # Bank
LOC = F27 | IOSTANDARD=LVCMOS25; # Bank
LOC = G29 | IOSTANDARD=LVCMOS25; # Bank
LOC = F30 | IOSTANDARD=LVCMOS25; # Bank
LOC = H26 | IOSTANDARD=LVCMOS25; # Bank
LOC = H27 | IOSTANDARD=LVCMOS25; # Bank
LOC = H30 | IOSTANDARD=LVCMOS25; # Bank
LOC = G30 | IOSTANDARD=LVCMOS25; # Bank
LOC = G25 | IOSTANDARD=LVCMOS25; # Bank
LOC = G19 | IOSTANDARD=LVCMOS25; # Bank
LOC = K18 | IOSTANDARD=LVCMOS25; # Bank
LOC = J18 | IOSTANDARD=LVCMOS25; # Bank
LOC = H20 | IOSTANDARD=LVCMOS25; # Bank
LOC = G20 | IOSTANDARD=LVCMOS25; # Bank
LOC = J17 | IOSTANDARD=LVCMOS25; # Bank
LOC = H17 | IOSTANDARD=LVCMOS25; # Bank
LOC = J19 | IOSTANDARD=LVCMOS25; # Bank
LOC = H19 | IOSTANDARD=LVCMOS25; # Bank
LOC = L17 | IOSTANDARD=LVCMOS25; # Bank
LOC = L18 | IOSTANDARD=LVCMOS25; # Bank
LOC = K19 | IOSTANDARD=LVCMOS25; # Bank
LOC = K20 | IOSTANDARD=LVCMOS25; # Bank
LOC = H21 | IOSTANDARD=LVCMOS25; # Bank
LOC = H22 | IOSTANDARD=LVCMOS25; # Bank
LOC = D21 | IOSTANDARD=LVCMOS25; # Bank
LOC = C21 | IOSTANDARD=LVCMOS25; # Bank
LOC = G22 | IOSTANDARD=LVCMOS25; # Bank
LOC = F22 | IOSTANDARD=LVCMOS25; # Bank
LOC = D22 | IOSTANDARD=LVCMOS25; # Bank
LOC = C22 | IOSTANDARD=LVCMOS25; # Bank
LOC = F21 | IOSTANDARD=LVCMOS25; # Bank
LOC = E21 | IOSTANDARD=LVCMOS25; # Bank
LOC = F20 | IOSTANDARD=LVCMOS25; # Bank
LOC = E20 | IOSTANDARD=LVCMOS25; # Bank
LOC = D17 | IOSTANDARD=LVCMOS25; # Bank
LOC = D18 | IOSTANDARD=LVCMOS25; # Bank
LOC = E19 | IOSTANDARD=LVCMOS25; # Bank
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15 VCCO - VCC2V5_FPGA - IO_L24P_T3_RS1_15
15 VCCO - VCC2V5_FPGA - IO_L24N_T3_RS0_15
15 VCCO - VCC2V5_FPGA - IO_25_15
16 VCCO - VADJ_FPGA - IO_0_16
16 VCCO - VADJ_FPGA - IO_L1P_T0_16
16 VCCO - VADJ_FPGA - IO_L1N_T0_16
16 VCCO - VADJ_FPGA - IO_L2P_T0_16
16 VCCO - VADJ_FPGA - IO_L2N_T0_16
16 VCCO - VADJ_FPGA - IO_L3P_T0_DQS_16
16 VCCO - VADJ_FPGA - IO_L3N_T0_DQS_16
16 VCCO - VADJ_FPGA - IO_L4P_T0_16
16 VCCO - VADJ_FPGA - IO_L4N_T0_16
16 VCCO - VADJ_FPGA - IO_L5P_T0_16
16 VCCO - VADJ_FPGA - IO_L5N_T0_16
16 VCCO - VADJ_FPGA - IO_L6P_T0_16
16 VCCO - VADJ_FPGA - IO_L6N_T0_VREF_16
16 VCCO - VADJ_FPGA - IO_L7P_T1_16
16 VCCO - VADJ_FPGA - IO_L7N_T1_16
16 VCCO - VADJ_FPGA - IO_L8P_T1_16
16 VCCO - VADJ_FPGA - IO_L8N_T1_16
16 VCCO - VADJ_FPGA - IO_L9P_T1_DQS_16
16 VCCO - VADJ_FPGA - IO_L9N_T1_DQS_16
16 VCCO - VADJ_FPGA - IO_L10P_T1_16
16 VCCO - VADJ_FPGA - IO_L10N_T1_16
16 VCCO - VADJ_FPGA - IO_L11P_T1_SRCC_16
16 VCCO - VADJ_FPGA - IO_L11N_T1_SRCC_16
16 VCCO - VADJ_FPGA - IO_L12P_T1_MRCC_16
16 VCCO - VADJ_FPGA - IO_L12N_T1_MRCC_16
16 VCCO - VADJ_FPGA - IO_L13P_T2_MRCC_16
16 VCCO - VADJ_FPGA - IO_L13N_T2_MRCC_16
16 VCCO - VADJ_FPGA - IO_L14P_T2_SRCC_16
16 VCCO - VADJ_FPGA - IO_L14N_T2_SRCC_16
16 VCCO - VADJ_FPGA - IO_L15P_T2_DQS_16
16 VCCO - VADJ_FPGA - IO_L15N_T2_DQS_16
16 VCCO - VADJ_FPGA - IO_L16P_T2_16
16 VCCO - VADJ_FPGA - IO_L16N_T2_16
16 VCCO - VADJ_FPGA - IO_L17P_T2_16
16 VCCO - VADJ_FPGA - IO_L17N_T2_16
16 VCCO - VADJ_FPGA - IO_L18P_T2_16
16 VCCO - VADJ_FPGA - IO_L18N_T2_16
16 VCCO - VADJ_FPGA - IO_L19P_T3_16
16 VCCO - VADJ_FPGA - IO_L19N_T3_VREF_16
16 VCCO - VADJ_FPGA - IO_L20P_T3_16
16 VCCO - VADJ_FPGA - IO_L20N_T3_16
16 VCCO - VADJ_FPGA - IO_L21P_T3_DQS_16
16 VCCO - VADJ_FPGA - IO_L21N_T3_DQS_16
16 VCCO - VADJ_FPGA - IO_L22P_T3_16
16 VCCO - VADJ_FPGA - IO_L22N_T3_16
16 VCCO - VADJ_FPGA - IO_L23P_T3_16
16 VCCO - VADJ_FPGA - IO_L23N_T3_16
16 VCCO - VADJ_FPGA - IO_L24P_T3_16
16 VCCO - VADJ_FPGA - IO_L24N_T3_16
16 VCCO - VADJ_FPGA - IO_25_16
17 VCCO - VADJ_FPGA - IO_0_17
17 VCCO - VADJ_FPGA - IO_L1P_T0_17
17 VCCO - VADJ_FPGA - IO_L1N_T0_17
17 VCCO - VADJ_FPGA - IO_L2P_T0_17
17 VCCO - VADJ_FPGA - IO_L2N_T0_17
17 VCCO - VADJ_FPGA - IO_L3P_T0_DQS_17
17 VCCO - VADJ_FPGA - IO_L3N_T0_DQS_17
17 VCCO - VADJ_FPGA - IO_L4P_T0_17
17 VCCO - VADJ_FPGA - IO_L4N_T0_17
17 VCCO - VADJ_FPGA - IO_L5P_T0_17
17 VCCO - VADJ_FPGA - IO_L5N_T0_17
17 VCCO - VADJ_FPGA - IO_L6P_T0_17
17 VCCO - VADJ_FPGA - IO_L6N_T0_VREF_17
17 VCCO - VADJ_FPGA - IO_L7P_T1_17
17 VCCO - VADJ_FPGA - IO_L7N_T1_17
17 VCCO - VADJ_FPGA - IO_L8P_T1_17
17 VCCO - VADJ_FPGA - IO_L8N_T1_17
17 VCCO - VADJ_FPGA - IO_L9P_T1_DQS_17
17 VCCO - VADJ_FPGA - IO_L9N_T1_DQS_17
17 VCCO - VADJ_FPGA - IO_L10P_T1_17
17 VCCO - VADJ_FPGA - IO_L10N_T1_17
17 VCCO - VADJ_FPGA - IO_L11P_T1_SRCC_17
17 VCCO - VADJ_FPGA - IO_L11N_T1_SRCC_17
17 VCCO - VADJ_FPGA - IO_L12P_T1_MRCC_17
17 VCCO - VADJ_FPGA - IO_L12N_T1_MRCC_17
17 VCCO - VADJ_FPGA - IO_L13P_T2_MRCC_17
17 VCCO - VADJ_FPGA - IO_L13N_T2_MRCC_17
17 VCCO - VADJ_FPGA - IO_L14P_T2_SRCC_17
KC705 Evaluation Board
UG810 (v1.3) May 10, 2013