Xilinx KC705 User Manual page 55

Connector Type:
•
For more information about SEAF series connectors see
HPC Connector J22
[Figure
The 400-pin HPC connector defined By the FMC specification
provides connectivity for up to:
•
•
•
•
•
The connections between the HPC connector at J22 and FPGA U1
subset of this connectivity:
•
•
•
•
•
The HPC signals are distributed across GTX Quads 116, 117, and 118. Each of these Quads
have their VCCO voltage connected to VADJ.
Note:
VADJ power sequencing logic described in the
Table 1-28: HPC Connections, J22 to FPGA U1
J22 Pin Net Name
A2 FMC_HPC_DP1_M2C_P
A3 FMC_HPC_DP1_M2C_N
A6 FMC_HPC_DP2_M2C_P
A7 FMC_HPC_DP2_M2C_N
A10 FMC_HPC_DP3_M2C_P
A11 FMC_HPC_DP3_M2C_N
A14 NC
A15 NC
A18 NC
A19 NC
KC705 Evaluation Board
UG810 (v1.3) May 10, 2013
Samtec SEAF Series, 1.27 mm (0.050 in) pitch. Mates with SEAM series connector
1-2, callout 30]
160 single-ended or 80 differential user-defined signals
10 GTX transceivers
2 GTX clocks
4 differential clocks
159 ground and 15 power connections
58 differential user defined pairs
• 34 LA pairs (LA00-LA33)
• 24 HA pairs (HA00-HA23)
4 GTX transceivers
1 GTX clock
2 differential clocks
159 ground and 15 power connections
The KC705 board VADJ voltage for the J22 and J2 connectors is determined by the FMC
FPGA U1
Pin
D6
D5
B6
B5
A8
A7
www.xilinx.com
[Ref
Power Management, page
J22 Pin Net Name
B1 NC
B4 NC
B5 NC
B8 NC
B9 NC
B12 NC
B13 NC
B16 NC
B17 NC
B20 FMC_HPC_GBTCLK1_M2C_P
Feature Descriptions
6].
(Figure B-1, page 73)
(Table 1-28) implement a
61.
FPGA U1
Pin
E8
55