Circuit Description Of Gy-2120 - Sony GY-2120WD Maintenance Manual

Circuit Description of GY-2120

. Refer to attached GY-2120 Block Diagram.
A BLOCK:
(1) Main System Controler
GY-2120's system control functions are performed
through System Controller CPU (SH-2). This CPU has
flash EEPROM whose firmware update is easily
performed.
The System controller main functions are as follows.
. SCSI controller management
. Data compression management
. Buffer memory management
. Sub code generation
. File management/table management
. Communication with OPTION IF CPU and SYS CPU
. Self-diagnostics
(2) SCSI Controller
For SCSI control an FAS366 (Q-Logic) is used.
In GY-2120, phase switching and data transmission
between buffer memory and SCSI bus, and interpreting
SCSI commands are performed by the system controller's
firmware.
During the Buffer memory's data writing, ECC is
appended (being that there are 64 data bits and 8 parity
bits). During buffer memory readout, ECC check is
performed.
B BLOCK:
(1) Data compression control
(2) Buffer Memory/Memory Controler
Buffer memory I/O bus is 72 bits width, (data=:64 bits and
parity:8 bits) Buffer memory is composed of 32 MB
*
DRAM
Logically this DRAM is divided into 8 banks of use.
In each tape track, user data is fixed by subcode from the
controller (CPU) and written by buffer memory. Also, the
system controller's firmware controls the 8 memory banks
upper switching memory area, the ECC block and data
transmission etc. 8 bit transmission of Buffer memory and
ECC encoder/ECC decoder transmission performed.
* Standard Memory Size is 32 MB. Factory option Buffer
Memory are 16 MB, 48 MB or 64 MB by the additional
board.
C BLOCK:
(1) ECC Encoder
Buffer memory data is received at this block where double
error correction code (Reed-Solomon code) is appended
and is the main function of the signals performed below.
. APPEND C2 ERROR CORRECTION CODE 27
bytes of C2 error correction (parity) code is appended
to 77 bytes of data.
. TAPE'S TRACK INTERLEAVING Product Array,
C1 data group substitution is performed from the
upper C2 data group. On the other hand, the tape's
upper 4 track segment's data is interleaved with the
C1 data group unit. Track interleaving and the
correction code's correction ability are a summed
process. When reading out from tape, 1 track segment
of data error is output, but in C2's correction circuit
data recovery is possible.
. APPEND SYNC BLOCK ID
. APPEND C1 ERROR CORRECTION CODE
To 192 bytes of data, 12 bytes of error correction
code are appended.
. RANDOMIZING
Every bit's 1/0 average is spread by pseudo-random
data numbers in order to improve the record
function's integrity.
(2) Word Interleaving
In the 4 SYNC BLOCK, 1 byte unit segment of data are
interleaved.
Word interleaving and C1 correction code's correction
ability have a summed process. When reading out from
tape, up to 20 bytes of consecutive errors is output, but in
C1's correction circuit data recovery is possible.
Further, from the ECC encoder's buffer memory input,
data is appended, parity check is performed, and
transmission error is sensed between the buffer memory
and the ECC encoder.
(3) ECC Decoder
Regarding the ECC decoder block, SYNC BLOCK
segments are output in the channel coding decoder and
perform the following processes.
. WORD REVERSE INTERLEAVE
. REVERSE RANDOMIZE
. C1 ERROR CORRECTION
. TRACK REVERSE INTERLEAVE
. C2 ERROR CORRECTION
8-2
In C1 error correction, 1 SYNC BLOCK has up to 5 bytes
of error data, then in the C2 column (77 bytes), up to 26
bytes of error correction is possible.
Furthermore, continuity check etc. is performed in the
decode (reverse interleaving and randomizing process)
block (except error segments) for sense stabilization.
ECC decoder's buffer memory writes 8 bit data and 1 bit of
parity is added.
This parity bit is from the SCSI controller's buffer
memory's data reading check.
(4) Channel Coding Encoder
From this block's ECC encoder block, 8 bits of data are
converted to 9 bits.
Also, the SYNC BLOCK's leading 4 bytes of signal is
appended. 8 to 9 bit conversion to the tape's record signal
is done so that long 0 or 1 bit strings become DC free. This
improves the record function's integrity.
(5) Channel Coding Decoder
In this block's SYNC signal sensing, data limits are
performed to the SYNC BLOCK segment. After that, 9 to
8 bit conversion (opposite of 8 to 9 bit conversion) is
performed, and a single 8 bit unit is restored.
D BLOCK:
(1) TTP System Controller
The TTP System Controller CPU (SYS CPU) performs the
following control functions.
. Communication with SCSI CPU and SERVO CPU
. Time code write/read control
. Tape write/read timing control
. Date read/write retry management
. Self-diagnostics
8-2
E BLOCK:
(1) READ/WRITE Amp Circuit
From the channel coding encoder's data, the serial signal is
converted by partial response class 4 (PR(1,0,-1)) signal
processing and becomes pre-code conditioned. This signal
is further scanned and put inside the write amplifier and
then written to the tape track for recall.
Further, from the read head, the output signal is decoded
by a read amplifier/equalizer, Viterbi's decoder circuit for
the channel coding decoder's input.
Under the servo block's control, the CTL signal and time
code signal each have a dedicated write Amplifier/read
amplifier. Write and read are performed on the tape's
longitudinal track.
F BLOCK:
(1) Servo
2 pieces of CPU are used. They are used for mechanical
system control (software servo algorithm method etc.),
2 Pieces of CPU control the following mechanical
system's control functions.
. Scanner rotation control
. Tape speed control
. CTL signal and SAT (Supplemental automatic
tracking) signal's
. Use for automatic tracking control
. Cassette tape thread/unthread control
. Tape tension control
. PEOT (physical end of tape), PBOT (physical
beginning of tape) sensors ETC. And the various
position sensors between, and Interface circuit.
. Reel, capstan, drum; signal interface circuit
GY-2120WD/WS