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1.6.2 Internal units
(1) CPU
Executes almost all instruction processing such as address calculation, arithmetic/logic operation, and data
transfer in 1 clock by using a 5-stage pipeline.
Dedicated hardware devices such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32 bits)
are provided to increase the speed of processing complicated instructions.
(2) Bus control unit (BCU)
Initiates the necessary number of external bus cycles based on the physical address obtained by the CPU.
If the CPU does not issue a request to start a bus cycle when an instruction is fetched from external memory
area, it generates a prefetch address to prefetch an instruction code. The prefetched instruction code is loaded
into the internal instruction queue.
(3) Internal ROM
The µ PD703008 and 703008Y incorporate mask ROM (128 Kbytes) and the µ PD70F3008 and 70F3008Y
incorporate flash memory (128 Kbytes). They are each mapped starting from address 00000000H. The
µ PD703006 does not contain internal ROM.
Access is enabled/disabled by the MODE0 to MODE2 pins. With the internal flash memory device, the
programming mode is specified by these two pins.
This internal ROM is accessed in 1 clock by the CPU when an instruction is fetched.
(4) Internal RAM
4 Kbytes RAM is mapped starting from address FFFFE000H. This RAM can be accessed in 1 clock by the
CPU when data is accessed.
(5) Interrupt controller (INTC)
Processes interrupt requests (NMI, INTP00 to INTP05, INTP10 to INTP14, INTP20 to INTP24, INTP30, and
INTP50 to INTP53) from the internal peripheral hardware and external sources. Eight levels of priorities can
be specified for these interrupt requests, and multiplexed processing control can be performed on an interrupt
source.
(6) Clock generator (CG)
By the internal PLL, supplies the CPU clock whose frequency is five times, one time (when internal PLL is
used), or 1/2 times (when internal PLL is not used) the frequency of the oscillator connected across the X1
and X2 pins. Input from an external clock source can also be referenced instead of using the oscillator.
(7) Real-time pulse unit (RPU)
Provides two 24-bit timer/event counter channels, six 16-bit interval timer channels, and capabilities for
measuring pulse width and generation of programmable pulse outputs.
(8) Serial interface (SIO)
The serial interface consists of 4 channels in total of asynchronous serial interfaces (UART) and synchronous
or clocked serial interfaces (CSI). One of these channels can be switched between UART and CSI, one channel
can be switched between CSI and I
fixed to CSI.
UART transfers data by using the TXD and RXD pins.
CSI transfers data by using the SO, SI, and SCK pins.
I
2
C transfers data by using the SDA and SCL pins.
The serial clock source can be selected from the baud rate generator output and system clock.
CHAPTER 1 INTRODUCTION
C ( µ PD703008Y and 70F3008Y only), and the other two channels are
2
User's Manual U11969EJ3V0UM00
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