Internal Rom Area - NEC mPD784225 Series User Manual

3.2 Internal ROM Area

The following products in the µ PD784225 Subseries have on-chip ROM that can store the programs and table data.
If the internal ROM area and internal data area overlap when the LOCATION 0H instruction is executed, the internal
data area becomes the access target. The overlapped internal ROM area cannot be accessed.
Part Number Internal ROM
µ PD784224 96 KB × 8 bits
µ PD784225
128 KB × 8 bits
µ PD78F4225
The internal ROM can be accessed at high speed. Usually, a fetch is at the same speed as an external ROM fetch.
By setting the IFCH bit of the memory expansion mode register (MM) (to 1), the high-speed fetch function is used.
An internal ROM fetch is a high-speed fetch (fetch in two system clocks in 2-byte units).
If an instruction execution cycle similar to the external ROM fetch is selected, waits are inserted by the wait function.
However, when a high-speed fetch is used, waits cannot be inserted for the internal ROM. Note that external waits
must not be set for the internal ROM area. If an external wait is set for the internal ROM area, the CPU enters a
deadlock state. The deadlock state is only released by a reset input.
RESET input causes an instruction execution cycle similar to the external ROM fetch cycle.
CHAPTER 3 CPU ARCHITECTURE
Access Space
LOCATION 0H Instruction
00000H to 0F0FFH
10000H to 17FFFH
00000H to 0EDFFH
10000H to 1FFFFH
User's Manual U12697EJ3V0UM
LOCATION 0FH Instruction
00000H to 17FFFH
00000H to 1FFFFH
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