Cyclic Data Assurance - Mitsubishi Electric MELSEC iQ-F FX5 Series User Manual

Cyclic data assurance

This function assures the cyclic data integrity in units of 32 bits or station-based units.
: Assured, : Not assured
Method
32-bit data assurance
Station-based block data
assurance
Interlock program
When a remote station is in the network, use station-based block data assurance. If it is disabled, the
functions of the remote station cannot be assured.
32-bit data assurance
Assures RWr and RWw data in 32-bit units.
■Data assurance at the time of access to link devices
When link refresh target devices are accessed, the integrity of 32-bit data can be assured by satisfying the following
conditions:
• The start device number of RWr and RWw is a multiple of 2
• The number of points assigned to RWr and RWw is a multiple of 2.
FX5 CPU module
Device
0H
2 words
(32 bits)
1H
2H
2 words
(32 bits)
3H
4H
2 words
5H (32 bits)
6H
2 words
(32 bits)
7H
■Data assurance at the time of access to buffer memory
The integrity of 32-bit data can be assured by satisfying the following conditions:
• Access using the DMOV instruction
• The start address of the buffer memory is a multiple of 2.
DMOV K100
4 FUNCTIONS
34
4.2 Cyclic Transmission
Description
Assures data in 32-bit units.
Data is automatically assured by satisfying assignment conditions of link
devices.
Assures data in station-based units.
Data is assured by enabling the station-based block data assurance in
the parameter setting.
Assures data of more than 32 bits.
Data is assured by configuring interlocks on programs.
Link refresh
U1\
G10240
DMOV instruction
FX5-CCLGN-MS
RWr, RWw
2 words
(32 bits)
2 words
(32 bits)
2 words
(32 bits)
2 words
(32 bits)
FX5-CCLGN-MS
Buffer memory
0H
2 words
(32 bits)
1H
2H
2 words
(32 bits)
3H
4H
2 words
(32 bits)
5H
6H
2 words
(32 bits)
7H
Link refresh Access to buffer
memory
 
 
 