Cyclic Data Integrity Assurance - Mitsubishi Electric MELSEC iQ-RJ71EN71 User Manual

Differences from link refresh
Item
Number of steps
*1
Processing speed

Cyclic data integrity assurance

*1 For actual values, refer to the following.
 MELSEC iQ-R Programming Manual (Instructions, Standard Functions/Function Blocks)
Shortening the link refresh time and transmission delay time
■Shortening the link refresh time
Remove infrequently used link devices from the link refresh range, and directly read or write the corresponding data using link
direct devices. This reduces the number of the link refresh points to the CPU module, resulting in a shorter link refresh time.
( Page 18 Link refresh)
■Shortening the transmission delay time
Because the link direct device allows direct reading or writing of data to the link devices of the master /local module at the time
of the instruction execution, the transmission delay time can be shortened.
Link refresh is executed in END processing of the sequence scan of the CPU module.
Precautions
■Cyclic data integrity assurance
Direct access to link devices does not provide station-based block data assurance. Use 32-bit data assurance, or if cyclic data
of more than 32 bits needs to be assured, use interlock programs. ( Page 23 Cyclic data integrity assurance)
■Mounting multiple modules of the same network number
When multiple master/local modules of the same network number are mounted, the target of direct access is the module
which has the smallest slot number in the base unit.
■Link direct device in a multiple CPU system
In a multiple CPU system, link direct devices cannot be used for the CC-Link IE Controller Network-equipped module
controlled by another CPU module.
Cyclic data integrity assurance
This function assures the cyclic data integrity in units of 32 bits or station-based units.
: Assured, : Not assured
Method Description
32-bit data assurance Assures data in 32-bit units.
Data is automatically assured by satisfying
assignment conditions of link devices.
Station-based block data Assures data in station-based units.
assurance Data is assured by enabling the station-based
block data assurance in the parameter setting.
Interlock program Assures data of more than 32 bits.
Data is assured by performing interlocks on
programs.
Access method
Link refresh
1 step
High speed
Available
Availability
Link refresh



Direct access
2 steps
Low speed
Not available
Direct access to Access to buffer
link devices memory
 
 
 
1 FUNCTIONS
1.1 Cyclic Transmission
1
23