Cyclic Data Assurance - Mitsubishi Electric MELSEC iQ-R Series User Manual

Cyclic data assurance

This function assures the cyclic data assurance in units of 32 bits or station-based units.
: Assured, : Not assured
Method Description
32-bit data assurance Assures data in 32-bit units.
Data is automatically assured by satisfying
assignment conditions of link devices.
Station-based block data Assures data in station-based units.
assurance Data is assured by enabling the station-based
block data assurance in the parameter setting.
Interlock program Assures data of more than 32 bits.
Data is assured by configuring interlocks on
programs.
When a remote station is in the network, use station-based block data assurance. If it is disabled, the
functions of the remote station cannot be assured.
32-bit data assurance
RWr, RWw, and LW data can be assured in 32-bit units.
■Data assurance at the time of direct access to link devices
When link refresh target devices are accessed, the 32-bit data can be assured by satisfying the following conditions:
• The start device number of RWr, RWw, and LW is a multiple of 2
• The number of points assigned to RWr, RWw, and LW is a multiple of 2.
CPU module
Device
0H
2 words
(32 bits)
1H
2H
2 words
(32 bits)
3H
4H
2 words
5H (32 bits)
6H
2 words
(32 bits)
7H
■Data assurance at the time of access to buffer memory
The 32-bit data can be assured by satisfying the following conditions:
• Access using the DMOV instruction
• The start address of the buffer memory is a multiple of 2.
U0\
DMOV K100 G10
RJ71GN11-T2
RWr, RWw, LW
2 words
(32 bits)
2 words
(32 bits)
Link refresh
2 words
(32 bits)
2 words
(32 bits)
DMOV instruction
Link refresh Direct access to
link devices
 
 
 
RJ71GN11-T2
Buffer memory
2 words 0H
(32 bits)
1H
2H
2 words
(32 bits)
3H
4H
2 words
(32 bits)
5H
2 words 6H
(32 bits)
7H
Access to buffer
memory



1 FUNCTIONS
35
1.1 Cyclic Transmission
1