Assurance Of Cyclic Data Integrity - Mitsubishi Electric MELSEC Q Series Reference Manual

4.1.5

Assurance of cyclic data integrity

This function allows cyclic data integrity to be assured in units of 32 bits or stations.
Assurance of cyclic data
32-bit data assurance
Station-based block data assurance
Interlock program
● Link scans are performed "asynchronously" with link refresh.
Therefore, when the following cyclic data of 32 bits or more are handled, new and old data may be mixed in units of 16
bits depending on the link refresh timing.
• Floating point data
• Present value or command speed value of a positioning module
Sequence scan
Link scan
● Even if latched device (listed in "CPU side device" in the table below) data are cleared to 0 by a sequence program at
power-on or reset of the CPU module, the latched data may be output depending on the timing of link scan and link
refresh.
For how to prevent output of latched device data, perform "Method for disabling output" listed in the table below.
Latch relay (L)
File register (R, ZR)
Extended data register (D)
(For Universal model QCPU only)
Extended link register (W)
(For Universal model QCPU only)
Device in the latch range
*1 For how to set an initial device value, refer to the following.
User's manual (Function Explanation, Program Fundamentals) for the CPU module used
76
integrity
0 END
Link refresh
CPU side device
Link refresh
0 END 0
Link refresh
Clear the value of the device to 0 using the initial device
*1
value .
Delete all latch range settings.
Direct access to link devices
Direct access
×
: Data assured, ×: Data not assured
END 0 END
Link refresh
Method for disabling output