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2 POWER SUPPLY, RESET, AND CLOCKS
2.4 Operating Mode
2.4.1 Initial Boot Sequence
Figure 2.4.1.1 shows the initial boot sequence after power is turned on.
Reset request from POR
(Initial SYSCLK)
Internal reset signal
SYSRST, H0, H1
S1C17 core
program counter (PC)
Note: The reset cancelation time at power-on varies according to the power rise time and reset request
cancelation time.
For the reset hold time t
RSTR
2.4.2 Transition between Operating Modes
State transitions between operating modes shown in Figure 2.4.2.1 take place in this IC.
RUN mode
RUN mode refers to the state in which the CPU is executing the program. A transition to this mode takes place
when the system reset request from the system reset controller is canceled. RUN mode is classified into "IOSC
RUN," "OSC1 RUN," "OSC3 RUN," and "EXOSC RUN" by the SYSCLK clock source.
HALT mode
When the CPU executes the halt instruction, it suspends program execution and stops operating. This state is
HALT mode. In this mode, the clock sources and peripheral circuits keep operating. This mode can be set while
no software processing is required and it reduces power consumption as compared with RUN mode. HALT
mode is classified into "IOSC HALT," "OSC1 HALT," "OSC3 HALT," and "EXOSC HALT" by the SYSCLK
clock source.
SLEEP mode
When the CPU executes the slp instruction, it suspends program execution and stops operating. This state is
SLEEP mode. In this mode, the clock sources stop operating as well. However, the clock source in which the
CLGOSC.IOSCSLPC/OSC1SLPC/OSC3SLPC/EXOSCSLPC bit is set to 0 keeps operating, so the peripheral
circuits with the clock being supplied can also operate. By setting this mode when no software processing and
peripheral circuit operations are required, power consumption can be less than HALT mode.
The RAM retains data even in SLEEP mode.
Note: The current consumption when a clock source is active in SLEEP mode by setting the CLGOSC.
IOSCSLPC/OSC1SLPC/OSC3SLPC/EXOSCSLPC bit to 0 is equivalent to the value in HALT
mode with the same clock source condition (refer to "Current Consumption, Current consump-
tion in HALT mode I
DEBUG mode
When a debug interrupt occurs, the CPU enters DEBUG mode. DEBUG mode is canceled when the retd in-
struction is executed. For more information on DEBUG mode, refer to "Debugger" in the "CPU and Debugger"
chapter.
2-14
V
DD
Undefined
IOSCCLK
Undefined
Figure 2.4.1.1 Initial Boot Sequence
, refer to "Reset hold circuit characteristics" in the "Electrical Characteristics" chapter.
, I
, and I
HALT1
HALT2
HALT3
Seiko Epson Corporation
Cancel reset request
Reset hold time t
RSTR
∗1
∗1: Reset vector (reset handler start address)
∗2: Address (reset vector + 2)
" in the "Electrical Characteristics" chapter).
Cancel reset request
∗2
S1C17W14/W16 TECHNICAL MANUAL
(Rev. 1.2)
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