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(1) When the CLGSCLK.WUPMD bit = 0
SYSCLK
(CPU operating clock)
CLGSCLK.CLKSRC[1:0] = 0x2 (OSC3)
CLGSCLK.WUPSRC[1:0] = 0x2 (OSC3)
(2) When the CLGSCLK.WUPMD bit = 1 and the CLGSCLK.WUPSRC[1:0] bits = 0x0
SYSCLK
(CPU operating clock)
CLGSCLK.CLKSRC[1:0] = 0x2 (OSC3)
CLGSCLK.WUPSRC[1:0] = 0x0 (IOSC)
Clock external output (FOUT)
The FOUT pin can output the clock generated by a clock source or its divided clock to outside the IC. This al-
lows monitoring the oscillation frequency of the oscillator circuit or supplying an operating clock to external
ICs. Follow the procedure shown below to start clock external output.
1. Assign the FOUT function to the port.
2. Configure the following CLGFOUT register bits:
- CLGFOUT.FOUTSRC[1:0] bits
- CLGFOUT.FOUTDIV[2:0] bits
- Set the CLGFOUT.FOUTEN bit to 1. (Enable clock external output)
2.4 Operating Mode
2.4.1 Initial Boot Sequence
Figure 2.4.1.1 shows the initial boot sequence after power is turned on.
Reset request from POR
(Initial SYSCLK)
Internal reset signal
SYSRST, H0, H1
S1C17 core
program counter (PC)
Note: The reset cancelation time at power-on varies according to the power rise time and reset request
cancelation time.
For the reset hold time t
RSTR
S1C17M12/M13 TECHNICAL MANUAL
(Rev. 1.2)
OSC3CLK
(CPU stop, CLK stop)
Executing the
slp instruction
OSC3CLK
(CPU stop, CLK stop)
Executing the
slp instruction
Figure 2.3.4.4 Clock Control Example at SLEEP Cancelation
(Refer to the "I/O Ports" chapter.)
(Select clock source)
(Set clock division ratio)
V
DD
Undefined
IOSCCLK
Undefined
Figure 2.4.1.1 Initial Boot Sequence
, refer to "Reset hold circuit characteristics" in the "Electrical Characteristics" chapter.
Seiko Epson Corporation
2 POWER SUPPLY, RESET, AND CLOCKS
Oscillation stabilization waiting time
SLEEP mode
Interrupt
(Wake-up)
∗ Starting up with the same clock as one
that used before SLEEP mode was entered.
SLEEP mode
IOSCCLK
(Unstable)
Interrupt
(Wake-up)
CLGSCLK.CLKSRC[1:0] = 0x0 (IOSC)
CLGSCLK.WUPSRC[1:0] = 0x0 (IOSC)
∗ Switching to IOSC that features fast
initiation allows high-speed processing.
Cancel reset request
Cancel reset request
Reset hold time t
RSTR
∗1
∗1: Reset vector (reset handler start address)
∗2: Address (reset vector + 2)
OSC3CLK
OSC3CLK
(Unstable)
IOSCCLK
∗2
2-9
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