Toshiba TLCS-900/H1 Series Manual page 538

(17) NAND flash controller (2/2)
Symbol Name Address
NAND
flash data
ND1FDTR 1D00H
transfer
register
NAND
flash
ND1FMCR mode 1CE4H
control
register
NAND
flash
ND1FSR 1CE8H
status
register
NAND
flash
ND1FISR interrupt 1CECH
status
register
NAND
flash
ND1FIMR interrupt 1CF0H
mask
register
NAND
flash
strobe
ND1FSPR 1CF4H
pulse
width
register
NAND
ND1FRSTR flash reset 1CF8H
register
NAND
flash ECC
ND1ECCRD 1CB0H
code
register
7 6 5
D7 D6 D5
Data window to read/write NAND flash
WE ECC1 ECC0
0 0 0
0: Disable ECC circuit
write 11 (at <CE>=X): Reset
operation 00 (at <CE>=1): Disable
1: Enable 01 (at <CE>=1): Enable
write 10 (at <CE>=1): Read
operation ECC data calculated
by NDFC
10 (at <CE>=0): Read ID
data
BUSY
R
Undefined
0: Ready
1: Busy
INTEN
R/W
0
0: Disable
1: Enable
D7 D6 D5
92CH21-536
4 3
D4 D3
R/W
Undefined
CE PCNT1
R/W
0 0
Chip Power Control
enable
0: Disable Always write "11"
( is
NDCE
high)
1: Enable
( is
NDCE
low)
SPW3
0
Pulse width for
= f
SYS
D4 D3
R
Data window to read ECC code
TMP92CH21
2 1 0
D2 D1 D0
PCNT0 ALE CLE
0 0 0
Address
Command
Latch Latch
Enable
Enable
0: Low 0: Low
1: High
1: High
RDY
R/W
0
Read:
1: Change
NDR/ B
Write:
1: Clear to
"0"
MRDY
R/W
0
Mask for
RDY
SPW2 SPW1 SPW0
R/W
0 0 0
,
NDRE NDWE
× (This register's value +1)
RST
R/W
0
Reset
controller
D2 D1 D0
2009-06-19