Toshiba TLCS-900/H1 Series Manual page 510

(3) Memory controller (1/3)
Symbol Name Address
BLOCK0
0140H
CS/WAIT
B0CSL (Prohibit
control
RMW)
register low
BLOCK0
0141H
CS/WAIT
B0CSH (Prohibit
control
RMW)
register high
BLOCK1
0144H
CS/WAIT
B1CSL (Prohibit
control
RMW)
register low
BLOCK1
0145H
CS/WAIT
B1CSH (Prohibit
control
RMW)
register high
BLOCK2
0148H
CS/WAIT
B2CSL (Prohibit
control
RMW)
register low
BLOCK2
0149H
CS/WAIT
B2CSH (Prohibit
control
RMW)
register high
7 6 5
B0WW2 B0WW1
W
0 1
Write waits
001: 0 waits
101: 2 waits
011: (1+ N) waits
111: 4 waits
Others: Reserved
− −
B0E
0 0 0
CS select Always Always
0: Disable write "0". write "0".
1: Enable
B1WW2 B1WW1
W
0 1
Write waits
001: 0 waits
101: 2 waits
011: (1+ N) waits
111: 4 waits
Others: Reserved
− −
B1E
0 0 0
CS select Always Always
0: Disable write "0". write "0".
1: Enable
B2WW2 B2WW1
W
0 1
Write waits
001: 0 waits
101: 2 waits
011: (1+ N) waits
111: 4 waits
Others: Reserved
−
B2E B2M
1 0 0
CS select 0: 16 MB Always
0: Disable 1: Sets write "0".
1: Enable area
92CH21-508
4 3
B0WW0
0
010: 1 wait
110: 3 waits
B0REC B0OM1
W
0 0
Dummy 00: ROM/SRAM
cycle 01: Reserved
0:No 10: Reserved
insert 11: Reserved
1: Insert
B1WW0
0
010: 1 wait
110: 3 waits
B1REC B1OM1
W
0 0
Dummy 00: ROM/SRAM
cycle 01: Reserved
0:No 10: Reserved
insert 11: SDRAM
1: Insert
B2WW0
0
010: 1 wait
110: 3 waits
B2REC B2OM1
W
0 0
Dummy 00: ROM/SRAM
cycle 01: Reserved
0:No 10: Reserved
insert 11: SDRAM
1: Insert
TMP92CH21
2 1 0
B0WR2 B0WR1 B0WR0
W
0 1 0
Read waits
001: 0 waits 010: 1 wait
101: 2 waits 110: 3 waits
011: (1+ N) waits
111: 4 waits
Others: Reserved
B0OM0 B0BUS1 B0BUS0
0 0/1 0/1
Data bus width
00: 8 bits
01: 16 bits
10: 32 bits
11: Reserved
B1WR2 B1WR1 B1WR0
W
0 1 0
Read waits
001: 0 waits 010: 1 wait
101: 2 waits 110: 3 waits
011: (1+ N) waits
111: 4 waits
Others: Reserved
B1OM0 B1BUS1 B1BUS0
0 0/1 0/1
Data bus width
00: 8 bits
01: 16 bits
10: 32 bits
11: Reserved
B2WR2 B2WR1 B2WR0
W
0 1 0
Read waits
001: 0 waits 010: 1 wait
101: 2 waits 110: 3 waits
011: (1+ N) waits
111: 4 waits
Others: Reserved
B2OM0 B2BUS1 B2BUS0
0 0/1 0/1
Data bus width
00: 8 bits
01: 16 bits
10: 32 bits
11: Reserved
2009-06-19